Partitioning Problem in FPGA and Its Embedded PC Core


I am currently working on scheduling / partitioning algorithms for Multi-Level Task handling using Xilinx Vertex II Pro. Do anybody know if some work have been done on partitioning algorithms for assignment of tasks to Embedded Microprocessor (embedded in FPGA - Xilinx Vertex II Pro) and FPGA it self.

Farhan A Chughtai Undergrad. University of Engineering and Technology,Lahore

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