Ray thanks for the answer! Searching this forum I also found your past
answers to this question.
You are missing some key pieces of information: the available clock
frequency
(this is different than the sample rate), and the target FPGA family.
The device is Virtex2 Pro. Its system clock is 108MHz or 125 MHz not decided
yet. And the filter coefficients are constant (not reconfigurable).
I have some additional question about FIR filter and its decimation
capability.
In my DDC after a CIC filter I would like to place this FIR filter, the
question is:
Is better to use FIR with decimation capability, or to use higher decimation
rate in CIC filter and use the FIR only as low pass filter?
CIC decimation is 32
FIR decimation is 4
The second way will allow me to do a time multiplex of this FIR because I
will have instead of 1/32 Fs the 1/128 Fs and also the number of taps will
be reduced, is this correct. Also this Fs is low enough to use MAC FIR.
Best regards, Sasa