sin3 filter for delta-sigma

If I use an isolated delta-sigma modulator, like a TI AMC1306 or something, to pick off the signal on a current shunt, we'd build a sinc3 filter into an FPGA to make the data stream into, say, 16 bit parallel form. The d-s converter would run at maybe 20 MHz, and I could probably get 16-bit digitizing with about 150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output sample rate? I see appnotes that specify output sample rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

Reply to
John Larkin
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tirsdag den 10. september 2019 kl. 22.00.29 UTC+2 skrev John Larkin:

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Reply to
Lasse Langwadt Christensen

This is a nice chip,

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but figs 25 and 31 sure don't help.

Reply to
John Larkin

Careful with the sidelobes. they all alias into the passband, so those filters look better than they actually are.

Reply to
Johann Klammer

I need to send the d-s signals into my FPGA, then do the sinc3 filtering, then the signal math. But I also want to send the analog signals out to some monitor BNC connectors on the front panel. Rather than coming back out of the FPGA with DACs, why not analog filter the delta-sigma stream outside the FPGA? That wouldn't have the sidelobes. The lowpass would just have to cut off sorta below the noise shaping region of the modulator, and only needs to look good on a scope, so that shouldn't be difficult.

One might even imagine recovering the delta-sigma signal with a good analog filter, then digitizing it into the FPGA. Or using some sort of digital lowpass filter in the FPGA that's not sinc3.

Actually, my signals will be mostly low frequency sine waves, or chopped-up low frequency sines, so aliasing into the upper lobes of the filter wouldn't be a big problem.

Reply to
jlarkin

onsdag den 11. september 2019 kl. 16.52.59 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

if you want analog out you might as well just lowpass the stream directly

silly to go analog and then back to digital, if you have room in the FPGA you can use a "proper" filter, the advantage of a CIC sinc3 filter is that it only needs few adders and registers

Reply to
Lasse Langwadt Christensen

Exactly. A dumb 3rd order sallen-key should do it.

Right, sinc3 might not be the best filter. We'll have gobs of resources in the FPGA.

Maybe I'll Spice the delta-sigma modulator just for fun, and play with analog filters. But it might take ages to run.

Reply to
jlarkin

I'm not sure what you are missing. The sigma-delta stage produces a 1 bit stream at your oversample rate. The filtering decimates and produces a wid er word with more resolution. You can pick off samples every 50 ns, but th ey won't be 16 bits. The way they get the wider word is to decimate in the filter combining input samples to provide more resolution in the lower sam ple rate output.

If you'd like to filter without decimating, you will end up with a smaller bandwidth but no additional resolution.

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Rick C

iptechnology.com:

put

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Run the delta-sigma filter in a VHDL simulation. It's a simple circuit and will run quickly. It's not hard to do analog filters in VHDL either. You just have to write a few equations and have them evaluated with an adequat e resolution. I've written simple RC filters this way.

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Reply to
Rick C

The filtering is necessary, but the decimation is optional.

Jeroen Belleman

Reply to
Jeroen Belleman

Right. A classic FIR filter has one input per clock and one output per same clock.

I may want to differentiate one of my signals, and would prefer that the filter output be as continuous as possible. Decimation makes big steps.

I have Verilog for a sinc3 filter. I'll have one of my FPGA kids figure out what it actually does, and why it decimates.

Reply to
jlarkin

Yeah, I suppose without the decimation you would get the additional resolution, but for a narrower bandwidth signal which is vastly oversampled. So yeah, the decimation is not required.

I guess I'm used to thinking the decimation is part of the filter. In reality it isn't. Thanks,

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Reply to
Rick C

It decimates because the higher sample rate is redundant. If the filter us es CIC it will need to be rewritten completely to remove the decimation. C IC is often followed by a FIR filter which sharpens up the band edges. The CIC filter will need to be replaced with a massive FIR with no actual mult iplies (in fact it seems to simplify to a box car filter) followed by a ful l speed version of the final FIR filter full of multiplies from the many, m any taps (original number of taps times the decimation rate).

If the differentiation does not require the final filter and that is only n eeded for the decimated output, the FIR can be implemented as a poly phase decimating filter which will be the same complexity as the existing FIR fil ter.

Another thought is to leave the filter as is and reconstruct the higher sam ple rate by interpolation. You may not need the full 20 MHz sample rate, s o you can set it to what you want.

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Rick C

torsdag den 12. september 2019 kl. 16.12.25 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

it is a CIC filter, integrators followed by differentiators

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if you don't decimate before the differentiators you need OSR times more memory in the differentiators

Reply to
Lasse Langwadt Christensen

iptechnology.com:

re1.PNG

memory

If you aren't decimating doesn't a CIC filter become a boxcar average? Yes , I see Wikipedia refers to the CIC as "an efficient implementation of a mo ving-average filter". So that is just N delay elements and N adders. Or i t can be done with fewer adders by simply adding in the latest sample and s ubtracting out the oldest on each iteration.

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Rick C

torsdag den 12. september 2019 kl. 22.01.38 UTC+2 skrev Rick C:

Or it can be done with fewer adders by simply adding in the latest sample and subtracting out the oldest on each iteration.

yep, that is what it does in a clever way that avoids the long delay line for "oldest"

Reply to
Lasse Langwadt Christensen

e and subtracting out the oldest on each iteration.

The delay line is there, it's just not so long and has adders as well. It' s the decimation that allows it to be log2(N) long rather than N. Just lik e in a polyphase FIR filter it saves the calculations you won't be needing to produce a result. If you remove the decimation a polyphase FIR becomes a standard FIR calculated in sections.

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Rick C

torsdag den 12. september 2019 kl. 22.42.44 UTC+2 skrev Rick C:

ple and subtracting out the oldest on each iteration.

ne

t's the decimation that allows it to be log2(N) long rather than N. Just l ike in a polyphase FIR filter it saves the calculations you won't be needin g to produce a result. If you remove the decimation a polyphase FIR become s a standard FIR calculated in sections.

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1.PNG

with the rate change moved to before the combs the delays is one sample at the output rate instead of R samples at the input rate

Reply to
Lasse Langwadt Christensen

ample and subtracting out the oldest on each iteration.

line

It's the decimation that allows it to be log2(N) long rather than N. Just like in a polyphase FIR filter it saves the calculations you won't be need ing to produce a result. If you remove the decimation a polyphase FIR beco mes a standard FIR calculated in sections.

re1.PNG

t the output rate instead of R samples at the input rate

And here I always thought the two were equivalent.

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Rick C

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