If I use an isolated delta-sigma modulator, like a TI AMC1306 or something, to pick off the signal on a current shunt, we'd build a sinc3 filter into an FPGA to make the data stream into, say, 16 bit parallel form. The d-s converter would run at maybe 20 MHz, and I could probably get 16-bit digitizing with about 150 KHz equivalent bandwidth.
If the sinc3 is (I think) essentially a FIR filter, is there an output sample rate? I see appnotes that specify output sample rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why isn't new filtered data available every 50 ns?
20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is OK, but why?My fpga/signals guy is ooo, or I'd ask him.