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delta-sigma again

I'm still playing with delta-sigma A/D conversion in LT Spice. I'll be using the ADUM7703 isolated 2nd order converter, clocked at 20 MHz, and we're thinking now about decimation filters in an FPGA.

Win was considering using a d-s encoder and an analog recovery filter.

My filter will be digital, and it will be inside a high-power control loop. The FPGA will drive a bunch of DACs at 500 KHz each, so if our d-s filter decimates it should deliver 500K samples per second to avoid squirrely aliasing hazards. I'd prefer it not decimate at all. I find the classic sinc3 recovery filter to be intellectually (ok, emotionally) repulsive.

In the model below, the recovered sine wave is pretty clean near zero volts and rattier at the peaks. I don't know if that's a real property of a d-s encoder, or some Spice numerical artifact.

Side story: one of my guys was plotting the frequency redponse of our class-D amplifier and got a nice curve with some weird, radical hickeys. Turns out he was signal averaging on a digital scope to remove the switching noise from the test sine wave, and reading the scope's computed RMS voltage to plot frequency response. But with some selected number of averaging samples, you get narrow frequency bands where the averaging rolls the async switching frequency back into visibility.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin
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Can you clock at say 16 MHz and then use a cascade of five half-band filter/decimators after each stage to get down to 500k? it's pretty efficient because half the taps of each filter have a zero coefficient and the tap requirements decrease as you go up the chain in frequency

This approach worked well for my wideband phase-shifter project a while back to get a near perfect 90 degree phase shift over the 300-4kHz audio band with only like 800 taps on the FIR Hilbert transformer when the signal was digitized at 96kHz, and about 40 more taps for a cascade of 3 half-band decimators to bring the effective sample rate down to 12kHz. Then I upsample and interpolate back to the system sampling rate for the DAC

Reply to
bitrex

Why decimate at all? To reduce the width of the data words?

I can simulate an R-C lowpass in one line of code, or a similarly simple chunk of FPGA hardware. I'd probably use 32 bit variables, which is easy. I could simulate my dumb RC-RC filter. That would make an IIR filter, which for some reason is not popular in FPGAs.

I do want a filter that won't create aliases, namely one that rolls off and stays rolled off.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin

Not sure what you are trying to say about "aliases". Filters don't create aliases. Decimation creates aliases.

Some filters have a monotonic stop band, others have stop band ripple. Is the ripple what you are talking about?

If you don't want to decimate, don't decimate. That's pretty simple.

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  Rick C. 

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Reply to
Rick C

DAC

so use a regular FIR filter

Reply to
Lasse Langwadt Christensen

I'll preface by saying I'm not intimately familiar with how this kind of delta-sigma converter you're making with an external analog block and doing the loop in an FPGA is supposed to operate exactly, but...it sounds like your bandwidth of interest is only to 500k but you're getting 20MHz worth of samples.

you decimate because a sharp low-pass with good time-domain response at high sampling rate requires a large number of FPGA gates/compute cycles, but using a half-band filter/decimator block you perform an anti-aliasing and decimation as one unit reducing the effective sample rate, which relaxes the compute cycle requirement of the following stages.

In my phase-shifter example a 90 degree phase shifter with both good frequency and phase domain response wasn't possible over the bandwidth of interest at the 96kHz fixed sampling rate whatever off-the-shelf module's converters he got were feeding the DSP with, it would require all the FIR taps than the machine had available and it still was supposed to do other tasks besides phase shift.

I guess what I'm trying to say is if you have highly oversampled data already you can do better than running sinc3 over the whole bandwidth signal by cascading stages of low-pass-and-resample filters then re-calculating FIR coefficients on the following stages in the chain, at the effective halved sampling rate.

It's then not hard to get a very nice low-pass response in both the time and freq domain without a lot of hyper-optimization, you can kind of ball-park how many taps each succeeding stage will need via a power law like x^1.8 the previous stage, and it works out pretty good 20 minutes in Matlab can get there.

Reply to
bitrex

I'm looking at nearly a 1000:1 clock to cutoff ratio. That would be a giant FIR.

Again, why not use an integrator-based IIR? Essentially simulate a state-variable filter, or in my case two cascaded RC lowpasses?

B = B + K1 * (In-B)

Out = Out + K2 * (B - Out)

which in my case runs at 20 MHz, the delta-sigma clock rate.

If you get lucky, the multiplies can just be right shifts (the Ks will be small) but in a modern FPGA, MAC blocks are free so we may as well do real multiplies.

I've done this in software several times, and it works fine, but FPGA guys seem to be hostile to IIR filters. Too simple to be much fun, I assume.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin

Given the hardware realities, it looks like my loop bandwidth will be in the ballpark of 50 KHz. I'll have a 250 watt sine wave source that I want to program the impedance of. I can do some of that with a real inductor, and synthesize the rest.

Why not a simple IIR filter clocked at 20 MHz? I don't understand why that is rarely done.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin

Filter and re-sample in stages!

FIRs can be designed and optimized using out-of-the-box functions in Matlab's signal processing toolkit there's not a great challenge to it once you settle on the requirements and a processing chain for the application. that's nice for people who like to get shit done

Reply to
bitrex

Usually people don't have the luxury of such a large oversampling bandwidth with respect to the pass band, and finding the optimal analog prototype for an IIR for a more bandwidth constrained situation can be difficult same as designing analog feedback filters. With FIR you can use tools that given a set of requirements can quickly compute the optimal coefficients and assure you that it's the mathematically-best you can get for those specs.

On resource-constrained processors or when the delay introduced by a long FIR is unacceptable sometimes you must go IIR to get a job done. If you have a 1000:1 sampling to bandwith ratio and a two pole RCRC IIR prototype or something gives you the response you need yes, why not but

1000:1 is very luxurious :)
Reply to
bitrex

Delta-sigma necessarily needs a lot of filtering. It slams full scale amplitude every sample!

I'm simulating my control system in Spice, all analog, but it will be mostly FPGA in real life, with delta-sigma ADCs and serial DACs, so I'd prefer digital filtering that behaves as much as possible like the analog stuff in my model. The IIR bits, I can understand.

My super math jocks are busy on other things right now, so I need to keep this klunky and reliable.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin

For FIR filters Matlab has several functions ("remez") in the signal processing toolbox to find optimal response filters for a set of stop and passband parameters, using the "Remez exchange algorithm":

What it's doing exactly under the hood I don't completely understand but if your inputs are reasonable it will very quickly spit out a set of coefficents you can then also plot and eyeball the response and quickly build up a whole signal processing chain.

Reply to
bitrex

Quite the contrary, to increase the width. If you are sampling substantially faster than you need, you can get a number of additional free resolution bits. This is called processing gain.

A CIC would be so much more resource efficient than that approaches and it doesn't need a multiplier. The data stream slows down pretty fast, so it doesn't pay off to implement the structure directly in VHDL. Two RAMs and a bit of muxing/arithmetic circuitry will result in enormous resource saving. All you need is to devise the content of the microsequencer. Then you add a compensation FIR to correct the CIC lobes. CIC is a FIR as well, BTW.

Best regards, Piotr

Reply to
Piotr Wyderski

In one of my projects I am sampling 50Hz mains at 1.5MS/s. Just because I can. OK, I wanted to be able to detect overload conditions with sub-microsecond response time, but this could have been solved differently in the analog domain. But why should I make the analog path more complex, if good and fast SAR ADCs are available and relatively cheap? The resulting system is much simpler (assuming the number of parts on the PCB is the metric) and reliable.

If your margins are not razor-thin, there is no such thing anymore. Any modern FPGA will happily decimate multimegabit streams, hands down.

Best regards, Piotr

Reply to
Piotr Wyderski

The reason is that when the corner frequency of an IIR filter is a small fraction of the sampling frequency it becomes very difficult to implement it. The coefficients have to be specified to a ridiculous level of accuracy and the accumulator needs a large number of bits. If you get this wrong, the filter either has the wrong frequency response (if you are lucky) or it oscillates. Even worse, it may be stable while you are testing in the lab and then oscillate or latch up in the wild with an input waveform you hadn't thought of. I learned this the hard way a long time ago in a medical application. FIR filters, and decimation when necessary, suddenly become very attractive after such an experience. FIR filters are unconditionally stable. IIR filters are not.

John

Reply to
jrwalliker

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FIR filter have another advantage when decimating, you only have to calcula te the outputs you actually use, iow you can run it at the output rate not the input rate

Reply to
Lasse Langwadt Christensen

Those are not linear phase, so somewhat disliked by scope people. You seem to be interested in the freq response so it's maybe ok. The rolloff may not be all that step either.

Reply to
Johann Klammer

32 bits would be fine for my application.

I have seen "butterfly" IIR filters that needed insane coefficients.

A digital simulation of a first order RC is not going to oscillate! You have to avoid math end-arounds, of course, in 2nd order sections, but all digital filters have to be careful about that.

I've done 2nd order sections by digitally simulating a state-variable filter, namely two integrators and some adds. Actually, I got the design from Don Lancaster's Active Filter Cookbook, and scaled it into digital. Once you have stable 1st order and 2nd order sections, any filter is possible.

Amazon wants $53 for a used copy of Don's book!

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
jlarkin

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I thought you decimated in order to turn a fast stream of 1 bit samples int o a slow stream of N bit samples! If you filter to a more narrow bandwidth I suppose you end up with more bits in your samples, but with lots of redu ndancy due to the high sampling rate... which can be eliminated by decimati ng. In this situation, a fast stream of N bit samples is very redundant an d typically pointless unless you are trying to keep the sample rate high fo r some other purpose.

If you are discussing why use a given type of filter, that is a different d iscussion. You can use a narrow band FIR filter with decimation to get a g ood result. It is typically more expensive in terms of resources than a CI C filter because of the multiplies. A CIC filter has none. A decimating F IR filter still has to do multiplies even once you have reduced the calcula tions by including the decimation into the FIR filter. Decimating FIR filt ers can be done easily in FPGAs where many multipliers are available and of ten just sitting idle.

I recall an interview question where I was asked how many multiplies a CIC filter had. I was a bit puzzled by the question because anyone who knew an ything about a CIC filter knew they had none and I started to think I heard the question wrong. The interviewer was a bit embarrassed I think because that question was intended to trip up an interviewee. That's a bit of a s illy thing to do I think. But whatever.

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  Rick C. 

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Reply to
Rick C

IIR filters have problems with resolution/precision. A FIR filter is inher ently stable because there is no feedback. An IIR filter has feedback. Yo u pick a value of the coefficients for your filter, then round them off to suit the word width. This introduces deviations. The math has round off e rrors at each pass which introduces more deviations. Those effects are fed back into the filter which can result in instabilities.

An analog IIR is a pretty simple device. A digital one can be more complex to analyze and prove to work correctly.

If you want to consider using a FIR filter, remember that you can incorpora te the decimation into the filter and not calculate all the sample you are discarding.

If you aren't going to decimate, remember that your 20 MHz input stream are single bits where multiplies are AND gates and adds are very simple... wel l, until you try to add 1000 bits I guess.

You can also do the filter in stages. A FIR to band limit and decimate by

10, then 10 more, then 10 more and you have 1000:1 filtering and decimation without the horrendous 1000:1 filter all at once. I believe they call tha t multi-rate filtering. It's been a while since I've done much of this.

Still, the CIC approach usually gives good results if your input is at leas t crudely filtered as such delta-sigma inputs are. The CIC has a good null at Fs and each multiple (or it's more likely at Fs/2). The input filter h as knocked down the inputs at higher frequencies and what each stage folds into the pass band is fairly well attenuated. Often a FIR filter is used a t the end to clean up the pass band edges.

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  Rick C. 

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Reply to
Rick C

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