Hi, all:-
A bit of a long shot here, but does anyone know whether the inputs will float on the Xilinx CPLD parts will float when power is not applied or do they have a nasty protection structure to a supply pin?
And if so, what if I float the related Vccio pin-- will that allow the input current to be reduced to just leakage current?
I don't see any info in what appears to be the relevant document:
Best regards, Spehro Pefhany
-- "it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Some more words are said in the datasheet ds090.pdf, page 11, Power-Up Characteristics
For the protection structure, perhaps check with an ohmmeter/conduction tester on an unpowered board...
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Thanks.
I would in a NY minute, if I had one..
Best regards, Spehro Pefhany
-- "it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
I can't say for sure about the 3.3V version of the Coolrunner but I do know that there was no diode to the Vdd rail on the 5V parts. They seemed to have zener/thick-oxide like protection. The input didn't hit a hard limit as it passed Vcc+0.7 as a diode would. This doesn't mean your idea will work however. The input leakage current may rise quite a bit before the hard limit is hit.
-- -- kensmith@rahul.net forging knowledge
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