Which HDL?

Apart from behavioral languages such as systemC thats about it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best bet,its not perfect but its better than a poke in the eye with a sharp stick..

I agree.

If you want to implement the hardware I recomment either verilog or VHDL. AHDL is vendor specific while most vendor tools can deal with both verilog or vhdl or mixed.

So now between verilog and vhdl, I can hardly guide you. I don't know verilog but from what I've seen it's more concise than VHDL. The latter tends to be very verbose. However, I work only with vhdl and I'm happy, with generate you can write more "generic" code to be reused and it still syntetize well.

Finally, what ever you choose, never forget that you must decribe the hardware you want built and not the behavior you want implemented !

Sylvain

|> VHDL: very disappointing, the nicest part of Ada has ben removed. |> No support for anonymous types, stiff and annoying syntax, weak |> interface inference (needs explicit component specifications).

Hm, you can define components in packages and just "use" them. So you don't need to cut'n'paste the interface into each architecture. A lot of VHDL examples (esp. from the FPGA vendors) don't use packages, as it hides the port names and makes the instantiation examples harder to understand.

--
         Georg Acher, acher@in.tum.de
         http://wwwbode.in.tum.de/~acher
         "Oh no, not again !" The bowl of petunias

Only *just*... ;)

Mark

bits

Verilog 2001 does support generate. It also supports arrays of instances which are often easier to use than generate for many applications. Verilog is also very popular in the U.S. although it has fewer followers elsewhere. If you already know VHDL the more concise nature of Verilog may not be a big win, nor Verilog's similarity to C.

Another thing to remember about Verilog is that it is less rigid about type-checking. For example you can build designs where the size of a vector applied to a module port doesn't match the size in the module. This will only generate a warning - not an error, and warnings are easy to miss when the tools produce 100's of them.

Just my 2 cents.

Gabor

I thought VHDL was a poke in the eye with a sharp stick :->

I find Verilog a heck of a lot easier and results in more compact code vs. VHDL. Verilog-2001 seems to have what was missing between the last version and VHDL (generate, configurations, good file I/O, lots of other new stuff). AHDL was the easiest to write, but supported only by Altera, therefore no coded testbenching.

-- Pete

So I'll have a look at it.

Yes, this is a big disadvantage.

Best regards Piotr Wyderski

Thanks, I didn't know about that. Looks like one of my problems has been solved.

Best regards Piotr Wyderski

I would say that everyone else seems to manage in producing working designs without rewritting either vhdl or verilog,niether of them are meant to be a 'programming language' so aproaching them from the point of view of a programmer isnt the best way of looking at them.

Verilog and VHDL both tries to be many things at the same time, but at the core are specification languages. Programming languages are a special class of specification languages. That old "It's not a PL" is getting old as an excuse of either. Any decent first year student of programming languages looking at either would recognize many obvious deficiencies.

VHDL is excessively verbose and it's much praised type safety is designed in a way that forces way too many explicit type casts.

Verilog (which I know far better) is less verbose but is often too loose with what it allows. It's a mix of two models, schematic and behavioral, but it's impossible for any non-trivial design to be purely behavioral as the abstraction unit (the module) must be instantiated as a component and attached to wires and registers.

I've witnessed HW development at a Silly Valley startup and observed how Verilog was mostly used as assembly, generated by big (and IMO nasty) perl scripts. I take that as a statement to the fact that we need something better.

Tommy PS: For a certain class of problems, I like my own variant of Timogriffer-C: Hard-C

Genericity is not a programming language approach. This is an abstract concept, which is used by many programming languages, but is not a part of them. Moreover, it is much more useful in hardware specifications than in programming languages. However, its support in VHDL and Verilog is very restricted and annoying. So the only reasonable thing I can do is to create my own HDL and a translator to VHDL, to reuse existing tools. :-)

Best regards Piotr Wyderski

Before you create your own HDL, take a look at Confluence,

It's IMO much more advanced than Verilog or VHDL and generates FNF, which can be converted to all kinds of stuff including Verilog or VHDL. 3 lines of Confluence is equivalent to about 30 lines of VHDL in some cases (ie. component instantiation). I think there are problems with creating dual-ported RAMs though, but this is mostly because other vendor tools (ie. Quartus, ISE) inference structures from generic HDL is still pretty poor in some cases. This may no longer be the case, it's been awhile since I checked.

-- Pete

You might also check EVHDL, available at

Thomas Entner

Verilog 2001 still lacks the ability to define constants inside generates that are dependent on the generate index variable. Structural placement, eg assigning values to the RLOC constraints for placed instances, remains difficult to do with Verilog 2001, while it has been available with VHDL for quite a while. Also, I find that the type checking in VHDL is a life saver for designs that have a lot of arithmetic. If you are already comfortable with VHDL, you may very well find Verilog to be frustrating to use for designs that are more structural than behavioral.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

One other criterion to consider - is there an easily installable platform independant free implementation of a simulator available? Verilog wins on this one with Icarus.

And do your generic/generation magic with a scripting language that generates verilog as output. Then you are in control of your toolchain.

... apart from the synthesis tool of course :-)

Cheers

Mark

When will the FPGA vendors support system verilog? System Verilog adds structures to Verilog 2001, so you can say: bus.data, bus.addr, etc.

When will VCS support Verilog 2001? It lacks the ability to make parameterized modules if you use the new "ANSI" style declaration syntax:

module foo #(parameter WIDTH=10) // One other criterion to consider - is there an easily installable

--
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Whichever way you go, get the revised classic

HDL Chip Design, A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J Smith, published by Doone Publications.

I have the much earlier ASIC edition which compares 100 or more typical small problems such as datapaths, FSMs etc in V & V and with well drawn (hand, not machine IIRC) schematics of what's synthesized. It seems its been brought upto date with added C & FPGA stuff, must treat myself.

I prefer Verilog too inspite of its own wierdness and shortcomings, after all it was designed more at the wirehead level where VHDL came from the DOD as a committee language. Both langs are very bloated and you will likely use