query in constraining timing

Kumar,

It will help if you give more details. Are these I/O paths (Tsu or Tco)?, or core paths? Same clock? or Different clock? Basically, you first need to figure out what type of constraint (Tsu, Tco, Max Delay) you can use. Once you have that, you can either use wildcards to group all sources and all destinations, or you can use assignment groups (also known as timing groups) to group names you cannot group with simple wildcards (see "Using Assignment Groups" in

A few examples:

• Assuming ina, inb and inc driving rega, regb and regc: set_instance_assignment -from in* -to reg* -name TSU_REQUIREMENT

• Assuming rega, regb, and regc driving outa, outb, and outc: set_instance_assignment -from reg* -to out* -name TCO_REQUIREMENT

• Assuming rega[3..0] to regb[3..0] set_instance_assignment -from rega* -to regb* -name MAX_DELAY 5ns (note that you can also use SETUP_RELATIONSHIP instead of MAX_DELAY. See online help for difference)

Hope this helps.

- David Karchmer Altera

I have 12 paths starting from a clock and some combinational logic including delay chain .These logic goes to output port of FPGA.My board engineer did mistake by connecting them some output to pins of VREF(high capacitive pins).The entire performance was in trouble.I cant change the board also now.I want to contraint from clock to output pin of FPGA so that i can get desired performance kumar

snipped-for-privacy@gmail.com wrote:

I have 12 paths starting from a clock and some combinational logic including delay chain .These logic goes to output port of FPGA.My board engineer did mistake by connecting them some output to pins of VREF(high capacitive pins).The entire performance was in trouble.I cant change the board also now.I want to contraint from clock to output pin of FPGA so that i can get desired performance kumar

snipped-for-privacy@gmail.com wrote:

How to know the values of (Tsu,Tco, Max Delay) in a design.I am using LVTTL I/O standard kumar

ram wrote: