when having a look at the TIMING REQUIREMENTS & OPTIONS I see that there are DELAY REQUIREMENTS with Tsu, Tco, Tpd, Th
and MINIMUM DELAY REQUIREMENTS with Tco, Tpd
What is the difference when defining these constraints ? Does these constraints make sense when having a multiclock system ?
When sampling an asynchronous signal coming into the FPGA how can I make the synthesis tool place the first flipflop of a synchronizing flip flop chain in a I/O register cell to improve Tsu ? Thanks in advance.
Hi Andre, Your best bet is to start reading the Timing Analysis section of the Quartus Handbook. It is extensive, has clear definitions and explains everything with good figures.
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Tco and Tpd are computed using the longest path:
- TPD: Tells the fitter to try to keep the longest path under the given value - TCO: Tells the fitter to try to keep longest Tco under the given value
Min Tco and Min Tpd are used computed using the shortest path - Min TPD: Tells the fitter to try to make all pin to pin paths (including shortest path) slower than this setting. - Min TCO: Tells the fitter to try to make all Tco paths (including shortest path) slower than this setting.
These constraints have nothing to do with multi-clock designs. They are simply easy ways to set global values.The way to constrain a complex multi-clock designs is to make instance specific Tsu/Th/Tco/etc constraints on each pin.
Quartus supports constraints similar to Primetime, where all I/Os are constrained by simply specifying external delays (basically specifying the Tco/MinTco of the chip driving the input pin of the FPGA and specifying the Tsu/Th of the chip the FPGA output pins drive to).
Assuming all clocks are constrained with a CLOCK_SETTING, you can use a MAX_DELAY -from -to to constrain the path such that the fitter will pack the register into the IOCell. You can also use fitter assignments to enforce the placement.The one that you will need is to apply the FAST_INPUT_REGISTER=ON to the register you want placed in the IO Cell.
You can also use a small Tsu constraint on that input pin, which should result in the same IOC placement, i.e. let the Fitter figure it out for you.
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