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Inversion of signals on synthesis

Dear Sir or Madam,

I have some phenomenon I do not know when synthesizing my VHDL description for my SRAM controller:

The .vho-file from Quartus is used for a timing simulation. When I have a look at internal signals of my controller like 'l_oe_bar', 'l_cs_bar','l_we_bar' I see in timing simulation with Modelsim that they are right inverted to my description, for example are they resetted to '0' and not to my declared '1' in the VHDL description.

The outputs of my controller are concurrently assigned like that:

OE_bar

Reply to
ALuPin
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Without actually looking at your files, assuming you are working with FPGA's it is very common that inverters disappear.

Active high or low makes no difference to a lookup table, the synthesis should generate equivalent logic, though the actual sign may change.

-- glen

Reply to
glen herrmannsfeldt

I have had this too with a project. When you do a functional simulation, everything is as you want it.

I thought this is a feature called "NOT gate push back", and can be turned off. It just a result of logic reduction. On the outside everything it is as it should be.

"ALuPin" schreef in bericht news: snipped-for-privacy@posting.google.com...

Reply to
Jeroen

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