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Inconsistant compilations with quartus

I are having truoble with quartus comiling my designs. I did a design in schematic and it worked correctly until I inserted a AHDL uart at witch time the uart was unstable every thing else worked fine. My supplier advised me that I shouldn't use the schematic as it doesn't compile properly and things can work one time and then do a small change and they do not the next. So I wrote it all out with his help in AHDL. Things eventually started to fall into place excpt that a have a very unstable design. sure the uart worked well but every time I compile it with a slight change the something else does not work properly. Conseqently I have no faith in AHDL file at all. The schematic still works fine without the uart. Has anybody else come accross this and do they have any solutions for the problem. Is it a common consencuse that schematic is not the method that should be used and AHDL or VHDl is the only reliable way to program these? I are using quartus 4.2 sp2 WE and flex6000 device.

Daniel

Reply to
Daniel
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Hi Daniel,

It's quite unlikely that this is a problem with the AHDL synthesis support in Quartus. That support is very extensively tested, and used by thousands of users, so it's much, much more likely that there is a problem with your UART design than a problem with the AHDL support in Quartus.

Usually "unstable" hardware that works sometimes and not others, or works on one compile and not others is due to race conditions or missed timing constraints in your design. Have you followed proper asynchronous design practice for all asynchronous transfers in your design? If you search this newsgroup, you'll find some pointers to good documents giving tutorials on asynchronous design.

Have you set timing constraints on all your synchronous transfers, and checked the Quartus timing report to be sure they were all met?

Are you using a disciplined reset scheme, or performing a recovery & removal timing analysis (see Quartus 4.2 help) to check your design will reset cleanly?

Vaughn Altera

Reply to
Vaughn Betz

Yes. Synchronous design and simulation before synthesis.

The schematic is not the main problem, it is logical and synchronization errors. You can fix unsynchronized inputs manually. From a schematic/AHDL source, Quartus can make a .vho netlist. You can then write a VHDL simulation testbench using modelsim, to find and fix the logical errors.

-- Mike Treseler

Reply to
Mike Treseler

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