Hi,
I have the following problem when using the Altera SignalTapII Embedded Logic Analyzer:
When compiling my design which includes a PLL generating a 48MHz and a
90 MHz clock out of a 30MHz clock there is everything fine.
When including the stp-file and then compiling the design again I get the warning:
# Critical warning: Timing requirements were not met. See Report window for details.
I thought that the SignalTapII would not influence the timing but it does. Why? What can I do about that?
The timing report shows the following critical path:
Clock Setup: 'pll1:PLL1_1|altpll:altpll_component|_clk1' -0.008 ns 90.00 MHz ( period = 11.111 ns ) N/A reg_help:REG_HELP_1|lpm_counter:l_little_count_rtl_1|cntr_ia7: auto_generated|safe_q[6] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[7] pll1:PLL1_1|altpll:altpll_component|_clk0 pll1:PLL1_1|altpll:altpll_component|_clk1 2
I would appreciate your help.
Thank you in advance.
Rgds