problem in timing simulation

Hi all,

The following piece of code works in functional simulation


--This process is used to detect the start condition(I2C).

-- SDA is used as the clock for this purpose

--************************************************************************* process(sda,sys_reset,current_i2c_state,scl) begin if(sys_reset='0' or current_i2c_state= I2C_HEADER)then detect_start

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While I don't know what your timing simulation problem is, I do have a suggestion (or maybe three). ;-) I would take "scl" out of the sensitivity list. You've described an asynchronous reset negative-edge triggered D-FF. The "scl" term isn't in the asynchronous reset logic or clock, so it shouldn't be in the sensitivity list. While this

*shouldn't* cause your problem, it will affect simulation performance. It may drive some simulators bonkers too.

The other thing that strikes me is the logic being done in the reset statement. I don' tknow the technology you're targeting here, but in many this is a no-no. The resets should be clean. Be careful with asynchronous resets too.

Maybe something like:

process(sda,sys_reset) begin if sys_reset='0' then detect_start

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Keith Williams

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