problem in timing simulation

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Hi all,

The following piece of code works in functional simulation
--This process is used to detect the start condition(I2C).
-- SDA is used as the clock for this purpose
  if(sys_reset='0' or current_i2c_state= I2C_HEADER)then
    detect_start <= '0';
  elsif(sda='0' and sda'event)then
    if(scl/= '0')then
      detect_start <= '1';
      detect_start <= '0';
    end if;
  end if;
end process;


In functional sim it works fine but when i do the timing simulation
even when the condition is satisfied the detct_start dosen't go high.

Note: This is the start detction logic for I2C .Since SCL and SDA are
externally pulled up '1' is converted to a 'Z'(not shown here).
But same is the case for funstional simulation.
the sda will aways be either '0' or 'Z' never a '1'.

I am using modelsim simuator to perform timing simulation .
and industry standard SDO file generated by altera.

Any suggestions appreciated.

Thanks in advance,

Re: problem in timing simulation says...
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While I don't know what your timing simulation problem is, I do have a
suggestion (or maybe three). ;-)  I would take "scl" out of the
sensitivity list.  You've described an asynchronous reset negative-edge
triggered D-FF.  The "scl" term isn't in the asynchronous reset logic
or clock, so it shouldn't be in the sensitivity list.  While this
*shouldn't* cause your problem, it will affect simulation performance.  
It may drive some simulators bonkers too.

The other thing that strikes me is the logic being done in the reset
statement.  I don' tknow the technology you're targeting here, but in
many this is a no-no.  The resets should be clean. Be careful with
asynchronous resets too.

Maybe something like:

  if sys_reset='0'
    then detect_start <= '0';
  elsif  sda='0' and sda'event   -- <== falling_edge(sda)
      if current_i2c_state = I2C_HEADER
          detect_start <= '0';
        elsif(scl/= '0')
            then detect_start <= '1';
            else detect_start <= '0';
      end if;
  end if;
end process;

This causes the current_i2c_state "reset" to be synchronous, but will
be more technology (and static timing analysis) friendly.

I also use the VHDL '93 riding_edge(), falling_edge(), functions
because they're easier for me to read.

OTOH, maybe a synchronous reset D-FF would be better:

   IF  falling_edge(sda)
       IF      sys_reset = '0'
           OR  current_i2c_state = I2C_HEADER
           detect_start <= '0';
         ELSIF(scl/= '0')
             THEN detect_start <= '1';
             THEN detect_start <= '0';
       END IF;
   END IF;


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