project navigator fails to detect inputs to the module

Dear All, I have recently started fpga programming. The problem I am facing is that I have made a module that has certain inputs but these inputs are not detected by the project navigaor i.e they dont appear in the constraint file automatically and when I try to connect them to an output by using NET "input" LOC = "P85";

Project Navigator gives an Error ERROR:NgdBuild:755 - Line 23 in 'FIR.ucf': Could not find net(s) 'next' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users).

Secondly, when I compile without constraint file everything works fine except that I get warnings All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic

but I have connected the outputs of this adder. The adder module heirarchy is as follows:

module fullAdder4X16Bit(a,b,c,d,cin0,cin1,sum,carryout0,carryout1); (top level) module fullAdder4X1Bit(a,b,c,d,cin0,cin1,sum,cout0,cout1); (called from fullAdder4X16Bit)

PLease help me in this regard.

Thanks Gul

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Atif Hashmi
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