Hi, there:
I am doing a design which only covers 10% of the slices...but after P&R, it spreaded all over the FPGA. How may I constrain it into, say, one corner...
How may I "nail down the logic into a known location"(Somebody told me this trick)?
BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't be used...
Kelvin
How about trying to constrain the design to NOT be placed in regions? Check the CONFIG PROHIBIT constraint in the online constraints guide. This could work for you.
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Apologies, I didn't read your post very carefully have you looked at this? http://www.xil> Xilinx Docs -> Constraint Guide -> AREA_GROUP
Thank you Chris.
I have read the xapp290... However I have defined AREA_GROUP on each modules of my design, now I need to restrain the P&R of a particular module to be within a corner of the module's AREA_GROUP instead...
Best Regards, Kelvin
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