When one is working on a development board one is often turning on parts of the board and turning off other parts. So when I tried to shut down one chip hanging off my Spartan 3 by basically doing nothing with its outputs I got this NgdBuild:755 Could not find net(s) error and it would not generate. It would seem to me if the synthesizer saw constraints not used in the source VHDL, it should possibly give a warning, but should be able to complete the design. PACE wouldn't open but I removed the outputs (that is: the FPGA inputs) from the constraint file with the text editor. This is remenisent of compilers that complain when a subroutine doesn't get called. I would like to enter all my board design IOs into the constraint file whether I use them or not.