S/w used : Xilinx WebPack Chip : Spartan - XC2S200PQ208C
I have configured a bus as a bi-direction by declaring it as 'inout' However on synthesizing the verilog files, the constraints editor shows some of the bus lines of the bus as BiDir and some as Tri Output
Is there any reason all the lines are not BiDir? What could have forced some of the line to become TriOutput?
S/w used : Xilinx WebPack Chip : Spartan - XC2S200PQ208C
I have configured a bus as a bi-direction by declaring it as 'inout' However on synthesizing the verilog files, the constraints editor shows some of the bus lines of the bus as BiDir and some as Tri Output
Is there any reason all the lines are not BiDir? What could have forced some of the line to become TriOutput?
If you never use the input of the bidir signal, it will be configured as a tristate output.
Yes if you have never used your INOUT pins as an input to your design then when you sysnthesize your code tool will automatically treated it as a tristated output only.
Sachin
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