I've got the Spartan-3 starter board, and in going through the ISE 7.1i documentation I see that there are "design elements" that can be used in a design. In some of those elements it says that they are "inferred rather than instantiated". For example, CC8CE for the Spartan 3 is a 8-, 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear. I had gone through the whole learning experience of creating a 32-bit binary counter using Verilog, and then I found that the CC8CE was "available". My question is, how are these available? I mean, in looking at my RTL schematic I'm not seeing that a CC8CE was synthesized. I also see the following in the synthesis report: ... Synthesizing Unit . Related source file is "myNbitCounter.v". WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. Found 16-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized.
Forgetting about the warning for now, I see that it recognizes my code as a 16 bit counter, but it didn't "infer" it to be a CC8CE type. Could I have somehow simply told it to use a CC8CE instead of going through the effort of creating my own (probably with errors) 16 bit counter? Isn't this such a basic element that I shouldn't have to re-create it?
Thanks for your assistance.