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Newbie question - using library "design elements"

I've got the Spartan-3 starter board, and in going through the ISE 7.1i documentation I see that there are "design elements" that can be used in a design. In some of those elements it says that they are "inferred rather than instantiated". For example, CC8CE for the Spartan 3 is a 8-, 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear. I had gone through the whole learning experience of creating a 32-bit binary counter using Verilog, and then I found that the CC8CE was "available". My question is, how are these available? I mean, in looking at my RTL schematic I'm not seeing that a CC8CE was synthesized. I also see the following in the synthesis report: ... Synthesizing Unit . Related source file is "myNbitCounter.v". WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. Found 16-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized.

Forgetting about the warning for now, I see that it recognizes my code as a 16 bit counter, but it didn't "infer" it to be a CC8CE type. Could I have somehow simply told it to use a CC8CE instead of going through the effort of creating my own (probably with errors) 16 bit counter? Isn't this such a basic element that I shouldn't have to re-create it?

Thanks for your assistance.

Reply to
Mike Oxlarge
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Mike

You can use the CC8CE as an instantiated component if that is what you want exactly. Details of the component are in the Xilinx Libraries Guide which you can assess from the documentation with ISE tools or from the Xilinx website.

Often if you want to infer a particular component you need to use a structure that the synthesiser lines up exactly to a expectation that the synthesiser has for that component. That is usually difficult to do and if you must have it then instantiate. CC8CE is also a macro element and not a primative so may not be inferred by the sythesiser for that reason. It may break your design down into smaller primative elements.

Generally I would be more concerned that Verilog description has the features that you need and is best checked with a simulator. Beyond that setting and meeting timing constraints should be your other concern.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board.

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Reply to
John Adair

Thanks for the speedy reply.

So what I'm taking from your response is:

  1. There is no way that I can simply say in my verilog code to use a CC8CE.
  2. If by chance, my verilog code matched what the synthesizer was expecting, then it _may_ use a CC8CE.

I understand that a counter in verilog is no big deal, but I'm having a tough time understanding why these design elements exist if there is no way to directly instantiate them. Like I said in my original post, I'm sure there are probably errors in my counter's design, so it would be nice to be able to "drop in" a known working element. In general, I think that this boils down to an issue of code-reuse, and me not yet at a point in my FPGA education of realizing how to take advantage of it. I'm hoping that I will learn that yes, there is a way to simply say "use this counter" or other design element, and feel confident that it was going to work.

Thanks again for your response, and happy Hogmanay.

Reply to
Mike Oxlarge

Mike

Point1- You can instantiate components including CC8CE. When you use them as components the synthesiser will normally consider them as a "black box" and does nothing to them. It will attach signals to ports as defined in your verilog.

Point2 - Spot on.

John Adair Enterpo>

Reply to
John Adair

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