First of all, I am a newbie to FPGAs and trying to learn the tools...I have had coursework in Verilog as it applies to ASICs, etc. I have an Insight Electronics FPGA Spartan II(100,000 gates) prototype board...it is a couple of years old. I am using the latest free Xilinx WebPack tools, etc.
The board came with the simple counter design already loaded and ready. You just put power to it and it starts counting. I don't have access to the Verilog code. I want to take the design, make a small change and reconfigure just to get a handle on the flow, etc. Is it possible to extract the .bit file from the ISP PROM and generate the source code via WebPack tools?
It appears that it can be configured by master serial mode via an ISP PROM. I have the JTAG header on the board and the JTAG cable. Do I just plug the JTAG cable into the PC's parallel port and the other end on the board, power-up the board and bring up the WebPack tools? The board has a switch that toggles the FPGA between "normal" and "configuration" modes. Without the JTAG plugged in, the switch just seems to reset the counter...
Thanks for any help....