how to start with development of eda tools

how to start with development of eda tools(e.g simulation tools and synthesizing tools): what knowledge should i know and where i can find the informations(tutorial, guides or something else)

thanks! br

Reply to
kevin
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  1. Review your digital logic design. Especially the combinational, synchronous sequential and state machine design. I say this because using the tools wouldn't make sense if you don't know the theory.
  2. You should have experience of building simple circuits with TTL chips. This will get you a physical feeling with gates, decoder, mux, flipflop etc.
  3. Buy an FPGA board. Get Spartan 3 kit (sold directly from Xilinx) or other FPGA boards from third party vendors such as Digilent or Xess.
  4. Start using your EDA tools, such as Xilinx Webpack. I would say you should start from Schematics first, then move to HDL. Don't start directly with HDL because it may misguide you to think that HDL is just like C. Doing schematics first also force you to think in term of hardware, not software. This will help later when you do your project with HDL.
  5. Learn either Verilog or VHDL. The book that I read to learn Verilog is Verilog HDL by Samir Palnitkar. It is the best Verilog book for beginner. I recommend Verilog because it is much easier to learn. VHDL is Very Hard and Difficult to Learn :-)
  6. Go back to your EDA tools and start using Verilog with the tools.

Some Useful URLs:

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: Free Xilinx EDA tools. Comes with simulator and synthesis tool.
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FPGA board vendor
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: Another FPGA board vendor
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: Spartan 3 Starter Kit
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: This website has some HDL projects to work with. xup.msu.edu : Xilinx University website. It has links to the EDA tutorials along with projects to work with your EDA tools.

Have fun!

Hendra

Reply to
Hendra

I agree, today students think more in software than in hardware. Therefore hardware has to be introduced. But only three points have to be respected, to *start* with HDLs:

- loops have to be expressed by the "process"-statement in VHDL (AFAIK "always" in Verilog)

- one bit is stored in a signal, assignments happen on a clock edge

- results of logic functions are assigned to signals, within the "process"-statement

Classical approaches teach logic elements and logic minimation, but this is counterproductive. Today you should think in logic functions (LUts) and not in gates, in vectors and not in shift registers.

Bye Tom.

Reply to
Thomas Reinemann

Hi Hendra:

Thanks for your reply!

But what you said seems how to use vhdl/verilog to do fpga design, but in fact, these are what i have been doing for years, and what interest me more now is the algorithms and principles of simulation and synthesizing, and i really want to make a tiny simulation tools(like simili) or synthszing tools, that's what i want :-).

Thank you again br

kevin

Reply to
kevin

start from

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?

vax, 9000

Reply to
vax, 9000

Are you saying that you want to make your own simulator and your own synthesis tool? Well, I don't know anything about that! Perhaps the LRM (Language Reference Manual) from IEEE may help you, because it is made more for the developer who makes the simulator and synthesis tool, rather than for the engineers who just use it.

Hendra

Reply to
Hendra

Thomas Reinemann wrote >

Why does the academic community still teach methods that are not used in the industry, such as K-Map?

Hendra

Reply to
Hendra

It's good to know what you want, but the playing field is large, so consider exploring a bit. Simulation attempts to answers the question:

"How can I predetermine that the hardware described by my HDL or netlist text will function as I expect without actually building and testing it."

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I expect that you will find that software tools like Simili are not as tiny as they might look.

Synthesis attempts to answer the question

"How can I build a physical logic circuit that will function exactly as predicted by the simulation of my hardware description text"

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Good luck.

-- Mike Treseler

Reply to
Mike Treseler

Personaly:

I think the first step for a eda tools must be a compiler which translate our vhdl or verilog codes to some intermediate format(like the binary format in modelsim), and then use some simulate and schedule algorithm and policy to do analysis and calucate, then get the result. So, I think they are the key to success.

this is just my personal opinion :-)

Reply to
kevin

I don't know the right translation, but I would it call mental or cerebral inertia. You are right, but youself said a beginner shall start with schematics. We all have been taught in this way. Just now these paradigms have to be replaced.

Bye Tom

Reply to
Thomas Reinemann

Why do we teach addition in first grade if everyone has hand calculators to do it?

I do think it is still useful to know how to at least simple logic minimization by hand. (In case you are lost on a desert island with a pile of TTL chips.)

It is useful to have at least some idea how much logic will be generated for different designs, or even if they are synthesizable at all. (FF's that trigger on both edges, for example.)

In many cases I prefer HDL to GUI schematic entry tools. It just takes too much work moving around little rectangles and getting all the lines to go the right way. It is nice to have a tool that will generate a schematic from HDL, though.

-- glen

Reply to
glen herrmannsfeldt

kevin wrote: > how to start with development of eda tools(e.g simulation tools and > synthesizing tools): what knowledge should i know and where i can find > the > informations(tutorial, guides or something else)

People have already given you the hardware experiences you'll need. Add to that list at least one graduate level course in compiler construction, and/or equivilent experience.

The techniques for how simulation engines work come from operations research (discrete event simulations) with a dose of queuing theory. Most digital simulators are to some degree simle discreet event simulations underneath. This sort of information should be relatively easy to find. (I had coursework and work experience to draw on here.)

The techniques for synthesis are deeply hidded from the public. It's probably easier to get documentation for building an atomic bomb:-) There are all kinds of books on combinational logic synthesis, but for synthesis of algorithms (i.e. sequential, behavioral code) the only book I can find is:

Logic Synthesis for Control Automata Samary Baranov Kluwer Acedemic Publishers

Of course, it makes no mention of behavioral, sequential code. You have to make the mental connections yourself.

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Reply to
Stephen Williams

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