Over the years I have taught myself Verilog and VHDL, and although I am qui te comfortable with Verilog, I feel as though my VHDL designs are just not as tight as they should be. In pursuit of self-improvement, I am trying to find "real world" examples of professional VHDL designs that I can glean f or hints on how to make my designs better. I have read many, many books and analyzed some projects on opencores, but everything that I have seen seems a bit lacking. I am hoping that the comp.arch.fpga community might share a few examples of solid VHDL designs that I can review. Incomplete designs are fine, as long as I can get a feel for how you are accomplishing things. Bear in mind that I will not critique your design, and am not interested i n participating in The Great HDL Debate MMXIV: Part XXIII. I need to contin ue to use both VHDL and Verilog.
- posted
9 years ago