(I'm not sure why, but Google apparently loses about 50% of my posts, so I'll try this again)
I have a few modules that I would provide to customers. They are all quite simple, but by not providing Veriog/VHDL I shelter them from the implementation details and possible warnings that would come from synthesis. So, I'd prefer to provide library "objects" in NGC format.
Most of the modules are 'internal' (not requiring IOBs), but one needs to map to IO pins, including an 8-bit bidirectional bus. If I -don't- include IOBs in the module, the parent design synthesizes OBUFs for the bidir bus and completely ignores the inputs. If I manually map the OBUFTs within the module, I get complaints during parent synthesis because apparently the parent is adding OBUFs which compete with the OBUFTs in the module.
I'd prefer a solution which requires as little 'extra' work on the parent side of things, but would appreciate any suggestions.