Post-Trasnlation Simulation using ModelSim in XST

Hi, I am trying to design a non-coherent DPSK demodulator as part of my RX chain of a DSP system in verilog. I have to target my design on a Vertex-4 development board (for prototyping purposes). Till now, I have designed my RX chain using two multiplier cores (I and Q multiplied with their delayed versions) and an adder core ((In)*(In-10) + (Qn)*(Qn-10)). When I simulate my design at the behavioural level everything's working fine. I synthesize my design, no warnings/ INFO/ errors. But, when I do a post-translate simulation, my Q-channel multiplier stops working. Moreover, when I MAP my design and do a post-map simulation, the design does not work at all. I get no warnings or errors in any of the processes Can anyone help me. If someone decides to be gracious, I can send you my archived project to look at. I have had this problem in the past and couldnt solve it. It may be my test-bench (as it is very simple)...but i just can figure it out. Any help will be appreciated....i am on a schedule and would like to keep my job....Lrd have MERCY!!! Thanks MORPHEUS