Post-Trasnlation Simulation using ModelSim in XST

Hi, I am trying to design a non-coherent DPSK demodulator as part of my RX chain of a DSP system in verilog. I have to target my design on a Vertex-4 development board (for prototyping purposes). Till now, I have designed my RX chain using two multiplier cores (I and Q multiplied with their delayed versions) and an adder core ((In)*(In-10) + (Qn)*(Qn-10)). When I simulate my design at the behavioural level everything's working fine. I synthesize my design, no warnings/ INFO/ errors. But, when I do a post-translate simulation, my Q-channel multiplier stops working. Moreover, when I MAP my design and do a post-map simulation, the design does not work at all. I get no warnings or errors in any of the processes Can anyone help me. If someone decides to be gracious, I can send you my archived project to look at. I have had this problem in the past and couldnt solve it. It may be my test-bench (as it is very simple)...but i just can figure it out. Any help will be appreciated....i am on a schedule and would like to keep my job....Lrd have MERCY!!! Thanks MORPHEUS

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morpheus
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Hi,

Hard to say what's wrong without further info...

A few wild ideas :

  • does the Technology View look fine ?
  • does the post-layout model look fine ?
  • when you load the design in the simulator, do you see all what you expect ?
  • sdf file correctly attached and assigned ?
  • simulation libraries okay ?
  • How are you vector applied wrt to clock ?
  • (async) Reset okay ?
  • Timing resolution 1 ps ?
  • Stimulus input timings realistic ?
  • sure you didn't recompile your Vital models with ModelSim XE version ??? (if that's what you're using)
  • Try & simulate a trivial stuff (just a mult for example)
  • "no warning no info" may not be a good sign (I'm joking here)

And after all, why are you so hot about post-layout simulation if you're reasonably sure of the sanity of your design ? If it's well-behaved, synchronous and all, and no scary synthesis warnings, HDL simulation fine, static timing analysis okay, and you're in a BIG hurry, then I would just keep things moving for now...

I hope it helps a tiny bit,

Best regards,

Bert

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