Hi all, I have a problem where my functional simulations are perfect, my timing constraints are all met, my post-par timing simulation doesn't violate any timing checks, but the results from my timing simulation are not the same as for my fuctional simulation.
I suspect the culprits are some multi-cycle paths that must not be so multi-cycle as I thought (if there are other possibilities, please let me know), and I was hoping to debug this by inserting delays on these paths to verify whether this is the case. I would use my post-par model, but it seems to take 3 days to run instead of the several hours for my functional model (Ahhh, to have a faster computer with more RAM!;)
I was therefore hoping to simply insert a simulation delay on these nets and was wondering what the best method might be? I'd prefer not to edit the VHDL code if possible, I was thinking along the lines of an SDF file, but this format seems more suited to structural code, since it only allows for delays between ports (since the NETDELAY keyword was removed from version 3.0).
Thanks in advance,