I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown identifier "X_ROC"* error. X_ROC is the only primitive that cannot be found in the SIMPRIM library provided with ActiveHDL. What is the standard procedure of getting up-to-date libraries: asking library sources from Xilinx or precompiled .lib file from Aldec? Simulator vendors somehow optimize pre-compiled libraries.
Getting up-to-date libraries for timing simulation
Jan 01, 2004
2 Replies
Consider writing your own vhdl code and siming it before synthesis.
-- Mike Treseler
Excuse me, what does this mean? BTW, I have resolved the problem by downloading last version (6.2) of SW from Aldec.
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