Compile 30% of my multipliers with LUT?

to

all

If you leave the sythesis tool to its own devices does it not use as many dedicated multipliers as it can then implement the rest combinatorially?

That's what I would have expected to happen.

Nial.

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board

Tell the synth that you are compiling for a smaller chip?

Looks to me that MULT_STYLE is an attribute as well as a synthesis option meaning you can either use it globally as it sounds you may have done or attach it on certain modules or certain signals to specify how to implement individual multipliers in your code. As a quick test, I wrote the following code and got one multiplier built from LUTs and the other using the MULT18X18S block:

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A; input [10:0] B; output [21:0] C; input CLK; input [10:0] X; input [10:0] Y; output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is lut; reg [21:0] Z; // synthesis attribute mult_style of Z is block;

always @(posedge CLK) Z

Thank you Brian! It seems to work with me.

Best Regards, Kelvin

However, the following code seemed fail...Maybe D & E are removed in the synthesis.

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A; input [10:0] B; output [21:0] C; input CLK; input [10:0] X; input [10:0] Y; output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is block; reg [21:0] Z; wire [21:0] D; wire [21:0] E;

assign D = X * Y; // synthesis attribute mult_style of D is lut; assign E = A * B; // synthesis attribute mult_style of E is block;

always @(posedge CLK) Z

never mind, it does apply to a wire also...Can test with these code...

assign D = A * Y; // synthesis attribute mult_style of D is lut; assign E = X * B; // synthesis attribute mult_style of E is block;