Hi:
I am using Xilinx Webpack and Modelsim XEII starter 5.7c to simulate Verilog.
If I put a `timescale directive in my uut, the compiler complains "module 'xxx' has a `timescale directive in effect, but previous modules do not."
If I don't put in a `timescale directive, then it makes the same message about the 'glbl' module.
Right now it gives peculiar results with the `timescale 10ns/1ns in my source, but simulates correctly without the directive. Trouble is, it has units of 1ps for each timestep without the directive.
How can I properly use the `timescale directive? This is only for functional simulation to learn Verilog. I know that things will get more complicated for synthesis for real devices.
Thanks for comments.
Good day!