I hope you had a relaxing Labor Day? Anyway, against my better judgement, I thought I'd have another go at this thread! Comments below.
Aha. Now we're getting somewhere. You seem to have shifted position from your previous post when you said about bypass capacitors:-
"That's not necessary. There's already so much plane-plane capacitance that the planes are already equipotential as far as the tiny charge injected by the signal trace can affect them."
At least you now seem to endorse the need for scattered caps. Progress indeed. ;-)
OK, from your other post in reply to Hal:-
As you appear to enjoy rubbishing the links I post up here to illustrate my points, and to keep you in practice, here's some more cannon fodder for you! I found a site online with a guy who's taken your advice and got out his scalpel and test equipment. (I hope you don't find this site dangerously moronic. ;-) )
Here
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is an experiment in which the ground plane cut is thin as compared to board thickness. Why don't his results match your invisibility prediction? (I agree that this doesn't show the ground plane shorted by a power plane, but you did say 'or'. I also wonder what is the situation you envisage that would have a ground plane break shorted by another plane?)
Next, here
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is an experiment in which a signal passes through a board and switches reference from one plane to another. The results would appear to disagree with your original assertion that vias and bypass caps are "not necessary". (Of course, now a 'scattering' is good!)
With tongue firmly in cheek, and with eager anticipation of your reply,
My results are different from his because we're doing totally different things. I'm TDRing microstrip traces on production multilayer boards, measuring impedances, reflection, and transmission; he's firing spark gaps at, essentially, home-made slot antennas. My measurements are quantified; his aren't.
"Shorted" in the AC sense, which merely requires a solid plane in a layer adjacent to the slit.
Bizarre. This guy can't even afford real pc boards, so has to fake it with wire and old copperclad. Fig 3 is hilarious; of course a signal radiates more on the side it's exposed to the antenna. Of course vias are inductive discontinuties.
As far as I can tell by TDR measurements, parallel planes in a PC board look like a perfect capacitor. I haven't been able to resolve any edge-echo effects, which would be associated with plane resonances. I assume that's because the parallel planes form a very low impedance transmission-line thing with low Q.
If you design an SMA connector into a multilayer pcb, which I occasionally do for amusement, you can TDR the planes. A typical plane will look like a perfect cap to 15 GHz, my limit of measurement. As you solder in bypass caps, the effective C goes up, irrespective of where you add the caps. That's true enough to make my stuff work:
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Caps are of course necessary to store energy, to handle the slow parts of load transients, since the plane capacitances are low, ballpark
100-200 pF per square inch. So it's easy to lay out boards with close power/ground planes and a scattering of ceramic bypass caps, 0.33 uF maybe, to break up any conjectured plane resonances (which I can't see!), and provide energy storage for the slow stuff. Just put some caps wherever convenient.
Look at it this way: if you use power planes and bypass caps to provide a stiff, wideband, low-impedance power supply to your chips, and you do it well, then there will be very little noise on any power pour relative to ground, even when it's whacked by big chip Vcc current spikes. So if the power plane is this equipotential to ground, why would a signal trace, switching "reference layer", notice that it's a different "reference"? The current poked into a plane by a signal zipping past is a minute fraction of the current spikes coming out of the power pin of a processor or an FPGA or even a CMOS gate.
If you're routing a long 3Gbps differential signal, then definitely you must have ground vias near every signal pair vias. Bypassing with a capacitor near an inductive vias has no effect. But using at least one ZBC plane in the stack it helps.
It would seem to me that it would go around the hole for the via. At least it could do that.
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With sufficient distributed capacitance, due to both the planes themselves and bypass capacitors, I would agree. Note that a plane still has capacitance even without another nearby plane. For a wide plane and a narrow wire, it is likely that the relative capacitance is fairly high.
As I'm sure you already know, this is because usually edge coupled signal pairs on a PCB are not 'proper' differential pairs the way (say) twisted pairs in CAT-5 are. The coupling between each distinct trace and the ground plane is much greater than the coupling between the pair of traces themselves. This is why Xilinx (and almost everyone else except, apparently, you) recommend this GSSG structure when passing high speed differential signals through vias. The vias reduce the common mode inductance of the transistion, which is, after all, essentially two single ended signals. (In fact the via is much more important for a single ended signal than a differential one, as a single ended signal is all 'common mode' and the ground via significantly reduces transition inductance.)
Today's hilariously bizarre link collection is here
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Read chapter 11 of UG076, and check out fig.11.10.
BTW., I saw the link you posted to your products. Thanks, they look great. I noticed that you chose to put them all in metal boxes or racks. Bearing in mind your philosophy on SI, I think that was a wise choice.
The GSSG structure makes sense in both those papers, not because it provides a "return current path" (which the papers, thankfully, don't say) but because it keeps the impedances of the traces constant as they burrow through the epoxy-glass, by providing uniform grounded capacitive loading. There is a difference.
That sort of thing matters at tens of gbps. It wouldn't matter if the signals were slow, a couple of hundred ps risetime or something pokey like that.
The V880 receives an optical data payload, phase locks to it, and fires any mix of eight delay generators, each of which makes delays of up to 3 seconds with 1 ps resolution. On board are power supplies, a pll, a uP crunching lots of code, and high-power electrical or laser output drivers. It mounts in a VME rack adjacent to various other boards, like Pentium SBCs, on 0.8" spacing, with no shields between. Jitter at the delayed outputs, relative to the master clock of the NIF timing system, averages maybe 3 ps RMS. There are no "return current" vias anywhere, and both single-ended and differential signals are "referenced" to any plane that's convenient.
I would call it glossing over certain issues. The current can obviously pass through the plane copper [because skin effect doesn't cause infinite impedance obviously], but it won't necessarily be a particularly low impedance path (depends on copper weight and signal speed, obviously) although it will be a short path ;)
For decently high speed signals (~ 50 psec rise/fall times) this issue _can_ hit the signal budget if there are enough excursions of the return path through the plane - not by much, but 'not much' is always dependent on the design. If you only have 1dB of budget (as exists in some standards I know), then this _can_ be an issue.
In 95% (or more) of cases, it's lost in the noise.
I agree, especially with the 'in extreme situations'. My view is it's dependent on the specific board. There's a reason we stitch planes along the side of a track (a subject in it's own right) in certain circumstances; the reason being to make sure the planes *really**are* equipotential (or damn close to it).
How about an SMA connector in the center of two parallel plane circles. If you know the dielectric constant you should be able to find the velocity, and then the resonant frequency. Other than two (or one) nice circle, it might not be a high-Q resonator. At (2/3)c, 5cm diameter circles should have a resonance around 9GHz.
If it is a differential signal, then you should not need to worry about ground bypassing. There should be no net ground current, that is the whole point of differential signaling.
I've put SMAs mostly on the power:ground planes, or smaller pours against ground, on VME boards, which are 6U Eurocards. I haven't observed anything on TDR that would correspond to an edge reflection, which would correspond to a plane resonance in the frequency domain.
A 5 cm diameter circle might resonate. I suppose the question is what would be the Q. Given a plane separation of, say, 6 mils, the effective impedance of the cavity might be so low that the resonance is swamped by FR4 dielectric and copper skin losses.
Multilayer inner-layer copper is usually etched (black oxide process) to improve adhesion and prevent delamination. That greatly increases skin losses at these sorts of frequencies, which is maybe why I'm not seeing plane resonances. Peel up some copper from a multilayer board: it's repulsive.
We did just get a spiffy 3 GHz spectrum analyzer with tracking generator, so I'll have to do a board with several SMA taps on a plane, and see what transmission behavior between connectors is like.
Has anybody seen, as opposed to simulated, plane resonances in a power:ground structure like this?
Consider a sphere with no other metal objects around it. Add some charge and compute the change in voltage. Divide, and that is the capacitance. It is a little harder to calculate for other shapes, but it is still there.
You can also do it by calculating the capacitance between two concentric spheres, in the limit as the outer one goes to infinity. Note that the parallel plate capacitor formula is only valid when the spacing is small compared to the size of the plates.
It should not matter how much coupling is between the pair, and from the pair to ground, as long as the coupling between each wire and ground is equal. Though just as important is to have a balanced source.
Hi John, Well, of course. I thought John L. was joking, because in the original article I posted a link for, the author goes on to explain that and says :- "Therefore, when a signal passes through a via and continues on the opposite side of the same plane a return current discontinuity does not exist. This is, therefore, the preferred way to route a critical signal if two routing layers must be used." That doesn't sound moronic to me. ;-) Cheers, Symon.
Hi Glen, I think it does matter in this case. I think we're agreed that the two signals that make up the pair are mainly coupled to the plane, not to each other. This means that current is flowing in the ground. As you say in another reply in this thread to me, that doesn't matter, UNTIL the signals come to a discontinuity in the 'signal to ground' coupling. Such a situation arises at the transition between layers, which is why the use of adjacent ground vias can mitigate the situation. HTH, Symon.
Hi John, So, if there's no return current, no current flows in the via right? **So you could disconnect one end of the via and it would not affect the operation of the curcuit?
It's important to realise that transmission lines are not just defined by capacitance. The structures have inductance also. It is an excess of this inductance that will slow down your signal. It is this inductance that is adjusted by the cunning placement of vias.
It is true that this sort of stuff only really matters at high speeds. However, modern FPGAs have sub ns rise time outputs whether you need that speed or not. This is why readers of this group should be interested.
HTH, Syms.
** My thanks to a friend for pointing this out to me!
p.s. Here's a nice article about plane inductance.
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