The signal is differential so when the return currents hit the wall, they cancel each other out at that border. There's no reflection because the common mode voltage isn't changing. If the differential signal wasn't routed differentially, then the reference currents would disperse when they hit the discontinuity and then eventually find each other or other ways to balance the current. Even though a large portion of the reference current is in the plane, the discontinuity results in almost no distance to travel for the differential reference currents to find peace.
A good point, I agree, that's true. As you say, there will be a discontinuity nevertheless, as the currents need to cancel out across the plane, but I would think this is a small effect. Furthermore, in that case, I think it means it is important to match the lengths of the traces from each termination to the vias as well as the total length of the individual traces. In the case where the extra ground vias are in place, that isn't so important.
Of course, the differential signal continues on its merry way through the vias. Without the ground vias, the transmission line impedance will have a significant discontinuity.
A transmission line is equivalent to a string of series Ls and shunt Cs. The Cs all end at "ground" for a single line, and there are additional Cs between lines for diff pairs. Of course all the Cs must be charged as a wavefront moves along the line. If that's what you want to call "return current" then do so. I call it the charging current of the capacitive component of the transmission line. The words aren't important. What's in question is whether a signal can dump its current into, say, a ground plane, hit a via, and then dump its charging current blips onto the other side of that plane, or into a sandwiched power plane, without bad things happening. My position is that planes, in real life, so close to equipotential, so firmly glued together by plane-plane capacitance and (at low frequencies) by bypass caps, that they all look like ground to the transmission line, so all the articles and "consultants" claims about managing "return current" are mostly a waste of words.
Gosh.
The GSSG ground vias do indeed moderate the inductance and capacitance of the signals as they scoot through the vias. Simulate and optimize for that. But they don't really serve to connect the planes so that the "return current" can find its way home.
No argument there. Some of the OnSemi ecl chips, and a couple of Analog Devices comparators, are also running around 35 ps edge rates, where things atart to get interesting.
His decoupling cap calculation in page 2, where he comes up with 20 uF, is typical of plugging numbers mindlessly into equations just because the dimensions seem to fit. The rest is similarly silly.
If a diff signal hits a region where the impedance changes, there will be a partial differential reflection, kicked back to the driver. Unless the driver is a matched impedance, which it generally ain't, the reflection will bounce off the driver and get tangled with the data stream, introducing jitter and closing up the data eye.
The differential impedance is determined by both signal-ground capacitance and signal-signal capacitance (which gets double credit). For a very fast edge, a diff signal that changes layers on vias can encounter a different impedance region and do some bouncing. The fast parts of the signal will tend to bounce back, and the slow parts will tend to pass forward, not good. The via structure can certainly be optimized for signal integrity. Above a few hundred ps risetime, it's generally not a big deal.
Just because a differential signal has some reference current in the cround plane doesn't mean the impedance control goes out the window if the ground return path is broken. Consider the lumped LC transmission line model recently referenced. There are Cs between the diff pair wires and from the wires to ground. Since the ground is common (unless your split runs underneath between the wires) these three Cs which were a delta configuration can be rearranged to a Y configuration. The single capacitor to ground should be at the common mode voltage level. You actually would like to get rid of steps in common mode, so any discontinuity in the common reference path is actually a *good* thing.
If one wanted to design two ground sections with an inch gap between the ground planes, the differential design could still work if the trace width and separation is changed over the gap. Referenced to a ground plane, the LC model has capacitors that include ground. For the ungrounded differential pair, the LC is entirely in the adjacent wires. The differential pair would make the transition from ground referenced to ground-free and back if the geometries are properly controlled for a proper transition.
Any arguement that return currents *are* necessary are harmed when the differential case is deemed as *requiring* the unbroken ground return current path. Keep in mind that the return current "pair" is complementary if the common mode is balanced.
The vast majority of 'differential signals' on PCBs are *not* true differential (balanced) signals. They need the reference plane (sometimes called ground which is really a little confusing) for return currents.
A balanced signal does not need a reference except it's inverse - that is NOT true of PCB differential signals in 99% of cases.
Break the return path and you break the impedance control - it really is that simple.
PeteS wrote: (snip on differential signals changing planes)
If you come in perpendicular to the plane split, there should not be any effect. The net current crossing the split in the signal conductors is zero, it also must be in the ground planes. That is, the currents in the ground plane are perpendicular to the signal wires.
Well, then they aren't differential.
Well, then the question is, is it close enough. I can't say.
Then it gets back to the non-differential case. There may or may not be enough capacitance around. What fraction of the current is common mode?
That is true, but it is separate from the question of crossing planes.
The length of the impedance discontinuity could (or should) be very short. If it gets back to the right impedance on the other side, the reflections will cancel. Again, separate from the question of split planes.
That depends on good board layout, but should be true. Especially one should be sure that the capacitance (per unit length) from the two to ground are equal.
For a true differential signal the ground plane current is perpendicular to the signal wires. Yes, that does depend on the conditions being close enough to the same for the two wires.
It is important that the impedance be the same on both sides. The length of the via itself should be much less than the wavelength, and so should have a relatively small effect.
I was thinking of the case where the signals stay in the same layer, but switch reference planes. If one is careful with the edges of the planes, it should be possible to minimize the discontinuity.
On the assumption that people aren't trolling, and to save people's time I would suggest that the Signal Integrity mailing list is perhaps a better place to continue. Everyone on that list has an interest in SI, so perhaps a more informed debate can continue. (Note: this is not saying that John or the other side is incorrect, just a suggestion)
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