Hi:
I'm making a 6-layer PCB for a TI DSP, fit onto a 168-pin SDRAM DIMM module form factor.
I'm trying to decide if I should stack the layers like:
- Top signal layer 2 signal
or
- Top signal
#1 is preferable for providing a tight coupling capacitor between the power planes, so when currents cross from top to bottom through vias, the displacement current doesn't have to spread out as far as if the power planes were more widely spaced.
The bad thing about #1 is that the traces on the outer and inner signal layers, will have different transmission line impedances for the same trace width due to differing separation distances from the power/GND planes. It also will take more care to ensure that traces on the adjacent signal layers don't parallel one another and get crosstalk.
#2 has consistent transmission line impedances, but the power and GND planes are much farther apart, resulting in much more of an impedance discontinuity for signals traversing a via from a signal layer referencing the GND layer to a signal layer referencing the 3.3V layer and vice/versa.
Any thoughts?
I also have to feed 1.8V to the DSP. I don't want to put any cuts in the 3.3V layer, as all the IO from the DSP module will be at 3.3V, so I don't want signals running over cuts in the 3.3V plane.
I'll probably put an island of copper on one of the inner signal layers for the 1.8V distribution to the chip. Hopefully that won't tie up too much routing real estate with at least 3 other layers available in that area.
Only 499 airwires to go...
It's funny how much I'll fuss to make a PCB very carefully. Yet the same chip is in a prototype system with 6 to 10 inch hookup wires running around in free space between three PCBs, and it works fine.
There are some things that the final system will do that the proto doesn't though, which are worth taking care about, like running the DSP's external CPU bus to an FPGA on another DIMM card, and possibly running the DSP and FPGA system synchronous by routing a clock from one to the other.