6-layer PCB stack up

Hi:

I'm making a 6-layer PCB for a TI DSP, fit onto a 168-pin SDRAM DIMM module form factor.

I'm trying to decide if I should stack the layers like:

  1. Top signal layer 2 signal
3.3V plane GND plane layer 5 signal Bottom signal

or

  1. Top signal
3.3V plane layer 2 signal layer 5 signal GND plane Bottom signal

#1 is preferable for providing a tight coupling capacitor between the power planes, so when currents cross from top to bottom through vias, the displacement current doesn't have to spread out as far as if the power planes were more widely spaced.

The bad thing about #1 is that the traces on the outer and inner signal layers, will have different transmission line impedances for the same trace width due to differing separation distances from the power/GND planes. It also will take more care to ensure that traces on the adjacent signal layers don't parallel one another and get crosstalk.

#2 has consistent transmission line impedances, but the power and GND planes are much farther apart, resulting in much more of an impedance discontinuity for signals traversing a via from a signal layer referencing the GND layer to a signal layer referencing the 3.3V layer and vice/versa.

Any thoughts?

I also have to feed 1.8V to the DSP. I don't want to put any cuts in the 3.3V layer, as all the IO from the DSP module will be at 3.3V, so I don't want signals running over cuts in the 3.3V plane.

I'll probably put an island of copper on one of the inner signal layers for the 1.8V distribution to the chip. Hopefully that won't tie up too much routing real estate with at least 3 other layers available in that area.

Only 499 airwires to go...

It's funny how much I'll fuss to make a PCB very carefully. Yet the same chip is in a prototype system with 6 to 10 inch hookup wires running around in free space between three PCBs, and it works fine.

There are some things that the final system will do that the proto doesn't though, which are worth taking care about, like running the DSP's external CPU bus to an FPGA on another DIMM card, and possibly running the DSP and FPGA system synchronous by routing a clock from one to the other.

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And, ideally, passing EMC. ;)

Cheers

Phil Hobbs

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Phil Hobbs

No problem; just adjust trace widths to keep the impedances what you want. Signals don't care what layer they are "referenced" to, if all the planes are equipotential, which they will be with reasonable bypassing.

#2 is OK, but I'd put ground on L2. And be careful about crosstalk.

Signals cruise right over plane cuts and never notice. We usually run several voltages on a power plane, and run matched-impedance traces on adjacent layers.

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John Larkin                  Highland Technology Inc
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John Larkin

All 'bad'.

top signal gnd main power (most commonly used power supply like 1.8V) signal misc power (3,3V, CPU core power supplies) signal

Never ever have 2 signal layers without a plane between them in these kind of design.

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Reply to
Nico Coesel

I agree, put the gnd layer next to the part on top. ( top signal layer is also the land pattern )

EMI can also radiate from the part die, so isolate it from other signals.

On 4 layer boards I create islands of power on the third layer, under the gnd layer.

Reply to
hamilton

Not necessarily,...

Where are your "cores" and "prepreg"? Thicknesses?

With three planes, like that, you'll have an odd stackup. You could easily get some pretty bad warping.

Not really that big of a deal, as long as the two are orthogonal to each other and fairly constant density. The other solution is to have non-impedance- matched signals on the levels away from the reference plane.

Reply to
krw

Nico Coesel schrieb:

Hello,

but routing of the signals might be difficult using 3 signal layers instead of 4. It may be possible to use one signal layer for vertical traces, one for horizontal traces and one for traces with 45 degrees direction. But using two layers for vertical traces and one for horizontal traces may result in crowded horizontal traces and a lot of free space between vertical traces. It depends on the shape of the board and the placement of the parts what configuration will be useful.

Bye

Reply to
Uwe Hercksen

You can use mostly horizontal traces on layer 1, and mostly vertical on layer 2, that way minimizes crosstalk. If you actually need controlled impedances, then you may have to restrict them to a single layer, or maybe mirror layers like #2 and #5, to be close to the power/gnd planes.

Jon

Reply to
Jon Elson

How about two 0V planes (layers 2 and 5)? I am starting a 6 layer board with low level signals and I am considering this option for extra sheilding between traces. If I can get the signals and power on 4 layers, are there downsides to using 2 0V planes, like return currents flowing in awkward ways?

Reply to
Nemo

It's hard to enforce direction discipline on layer 1. All the surface-mount parts shoot signals in all directions.

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John Larkin

The "return current" and "reference plane" things are mostly myth. A controlled-impedance trace can run adjacent to a power plane, or a plane with multiple pours, or between planes of almost any sort.

You can get into trouble running analog signals adjacent to power pour planes, in that power supply noise can couple into the signal traces. In that case, ground on 2 and 5 makes sense.

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John Larkin

See what the PCB maker offers :-)

But no controlled impedance on two layers! In my stackup you can have controlled impedance on any signal layer. If you use DDR memory and connect the memory with 2 signal layers which are not seperated by a plane it simply won't work (reliable).

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Reply to
Nico Coesel

Bad plan. A decent fab should be able to make the board to your spec.

That depends entirely on the layout. If the layers are spare, just calculate the impedance using the appropriate thickness. If it's dense, the wires underneath act as a plane. If it varies a lot, you're screwed. ;-)

I almost always have a mess of signals that don't need controlled impedance anyway.

But it'll warp, popping BGAs like popcorn.

Reply to
krw

That's a waste of a plane. Use voltage pours on one of them.

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krw

Reply to
Nemo

If you spend loads of cash or order >1000 pieces maybe. Better go with what is available. PCB makers offer a certain stackup for a reason: most customers want it.

Same here, but there are always a few signals that do need controlled impedances.

Never had that problem. Sounds more like a process control problem during soldering to me :-) Boards are likely to warp when heating up and cooling down during soldering are not properly controlled.

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Nico Coesel

No, even five, or so, panels. It's not expensive to get what you want. It is also important to get what you ask for. If you just take whatever the fab is selling today, you're in for some big surprises down the road.

other

So they go on the layers closest to the planes.

No, it's a problem with unbalanced stresses. Any decent layout guy will try to balance metal on opposing layers as well as possible. However, he has to know the exact build order (where the cores are and how it's laminated). Buying any old junk the fab happens to have laying around this week is a recipe for disaster.

Reply to
krw

Its not what the fab sells today. Its what they offer as a standard. If you want low volume and quick & cheap then pooling is the way to go. But you have to 'make do' with what they offer which most probably is be the best choice for most designs anyway.

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Reply to
Nico Coesel

And in another post:

To say that "return current" is a myth, flies in the face of considerable research, modeling, and empirical evidence. Not to mention the simple fact that circuits must be complete in order for any current to flow.

So perhaps you could elaborate on exactly what you mean?

As I understand, and this seems to be backed up by many papers, and even a few visual demonstrations, is that return current does indeed flow under a trace, in the nearest plane. If that signal hops to another layer which is closer to another plane, then the return current must also hop. It may do so through the distributed capacitance, through stitching vias (which can only be applied between planes which are equipotential at DC) or through bypass caps.

For signals switching between different DC voltage planes, then it is usually a combination of distributed capacitance and nearby bypass caps that accommodate the return current traversal between the planes, depending on frequency, the inductance of the bypass cap connections, and the spacing of the planes.

Every traversal represents an impedance discontinuity. An analogous situation would be to take a coax cable, and cut the shield all the way around, leaving a gap of about 1 mm.

You certainly wouldn't propose that such an interrupted cable functions normally?

It could be made to behave similarly to a PCB trace running over a slot or switching reference planes by taking a piece of hookup wire with a loop area large relative to the Z0 of the cable at a particular frequency, and soldering the two pieces of shield back together with the wire loop. Now we should be able to agree that the cable can once again carry DC current, but isn't its AC performance horribly degraded?

To say that these phenomena do not occur contradicts significant evidence to the contrary, such as what might be quickly revealed by a simple Google of "pcb trace return current"

Additionally, when a trace crosses a cut in a plane the return current must go around the cut.

I suspect what you are trying to say is that only under rare circumstances, the effects of allowing signals to jump layers and pass over cuts in planes is not deleterious enough to matter.

However, this would require qualifications with some sort of objective criteria.

Frankly, considering the amount of work you do with high speed signals, it surprises me that you make these statements, and that your work doesn't demand highly critical application of the techniques which you claim are bunk.

It would be interesting if you had the time to contribute to the research publications on this subject, if you have a way to show that current thinking (and models, and empirical experiments consistent with theory) are not entirely satisfactory.

Good day!

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What it flies in the face of is a lot of hearsay and opinion, and Howard Johnson's silly book.

I lay out test traces on multilayer boards, with SMAs on both ends, and TDR test them on a 20 GHz oscilloscope.

Not to mention

Consider a board with ground plane on layer 2, and a multiple-voltage power pour on layer 4. Assume a trace starts on L1, runs for a bit, vias to layer 3, meanders around, and returns to layer 1 to connect to some other chip.

At the start, the "return/reference" layer is L1, and it's a microstrip. Once it dives through the via, it becomes a layer 3 stripline. I assume you adjust the trace widths appropriately for whatever impedance you want.

Once it gets to layer 3, it sees a ground plane above and a power plane below. The power pours should have no huge amount of AC signal relative to ground, enforced by bypass caps and the considerable plane-plane capacitance. The microstrip doesn't know that it's not sandwiched between two grounds; it can't see the DC on the power pours, and they look like ground at AC.

The current associated with a signal traveling along a trace is tiny compared to the very low plane-plane impedance.

Sure, dielectrics get charged when the voltage on a trace changes. No harm done. The return-current thing is a philosophical dilemma that sells a lot of books and consulting hours. Ignore it and boards work fine.

If that signal hops to another

Which it does, easily. The whole plane structure looks equipotential to the trace.

It may do so through the distributed capacitance, through

Plane-plane capacitance is huge compared to trace-plane capacitance, because planes are big and traces are skinny. Bypasses are overkill.

Vias are small discontinities in the 100 ps domain. Most people don't work down there. If it matters, there are things you can do with the geometry.

I don't propose to design around analogies, either. A PC board is not a coaxial cable.

You can google about ghosts and free energy, too.

Not really. A narrow slit still has a lot of capacitance across the slit, and usually planes are capacitively coupled to adjacent planes. So not much voltage gets induced across a ground slit, especially at slow, nanosecond speeds. You can make a slotline antenna, which could radiate EMI if the trace edge were fast enough to excite it, but not much energy will be extracted from the signal.

Right.

Start to worry a little for edges below 100 ps.

It's because I design picosecond stuff that I make these statements.

All you need to do is make a multilayer board with some test traces, and TDR it. I do that often, if a board has room for a test trace and a couple of connectors.

I think it was Werner von Braun who said that one experiment is worth a thousand expert opinions.

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John Larkin         Highland Technology, Inc

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