I am trying to place and route my design to a specific portion of the FPGA by using the Xilinx modular design flow, coupled with AREA_GROUP constraints. But the par for a module gives the following error message for some (not all) region constraints.
FATAL_ERROR:Route:basrtareacst.c:891:184.108.40.206 - Failed to compute route area extrema. Process will terminate. To resolve this error, please consult the Answers Database and other online resources atIf you need further assistance, please open a Webcase by clicking on the "WebCase" link at
I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is:
INST "u1" AREA_GROUP=g1; AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3; AREA_GROUP g1 MODE=RECONFIG; AREA_GROUP g1 PLACE=CLOSED;
Could not find any help in the answers database at Xilinx. Can someone please help me?
Thanks in anticipation. Aman