Is there anybody who has experience at interfacing a WishBone IP core to a CoreConnect bus. Specifically the design of a bridge ?
regards,
Tom
Is there anybody who has experience at interfacing a WishBone IP core to a CoreConnect bus. Specifically the design of a bridge ?
regards,
Tom
No, but I would be very interested in such a thing! Opening up the whole opencores library to use with microblaze would be a great boost for both.
Regards,
John
An interesting aside for those using Altera products: The Avalon bus interface and Wishbone are close enough to each other to make this very simple.
A while ago I studied the feasibility of this using Avalon and the Ethernet MAC core on opencores.org. You can wire up a Wishbone slave to Avalon in the SOPC Builder tools with a few mouse clicks. No bus bridge required. Wishbone masters require a bit of RTL to implement their "acknowledge" signal but other than that everything falls together automatically.
Jesse Kempa Altera Corp. jkempa at altera dot com
Ok thanks for your reply but we are using a virtex pro with powerpc or microblaze. Trouble is as John said, we cannot use the free cores. So it would be nice to have a bridge.
regards,
Tom
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