Nios II Going Live...

Tomorrow is the big Nios II launch date, but info is already going up....

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Full 32bit. 2X-4X faster than Nios I and starts at only 500 LE's. New IDE. New Compact Flash and other periferals.... Can't wait to get a hold of it.

Ken

Reply to
Kenneth Land
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It seems that Altera has created a MicroBlaze as well. They have finally realized that a FPGA based soft processor should have

- 32 bit ISA

- 32 registers

- 3 operand instruction format

- JTAG based HW debugging

- HW divider

The weird register window mechanism from NIOS (is it called NIOS1 now?) didn't work well in embedded processing markets.

Göran Bilski

Kenneth Land wrote:

Reply to
Goran Bilski

I did hear that NIOS II was quite close to the MIPs CPU in structure/mindset....

-jg

Reply to
Jim Granville

And I heared that the old NIOS was a SPARC structure.

Reply to
Jeroen

Lol.. Because Xilinx invented RISC didn't they?

Well, you can hardly call it weird (at least one mainstream arch, SPARC, uses it), and in the embedded space, Tensilica have no problems selling their arch, which also features register windows.

If you really want to sling some mud, my favourite part is where they talk about "Avoiding processor obsolescence"... Er, hasn't this has just made NIOS obsolete? How long before they change their minds again?

Fair play to them, I didn't really think too much of NIOS, but if they really can push 200MHz with this, then I am impressed.

Cheers, JonB

Reply to
Jon Beniston

Just because it is used, doesn't mean its a good idea. Register windows suck. Register windows reinvented (rotating register file from the IA64 suck as well).

If you want fast function-call save/restore, observe that going into a cache or memory, you often have a wide interface, so the cost of writing 4 ALIGNED words is the same as writing one, and have aligned 4 or aligned 8 load/store instructions. Remember the FPGA mantra: Wires are cheap, switching the wires is expensive.

Nah, because NIOS1 will still be around. One of the great things about soft-cores is they are a bit easier to keep "in production" compared with a hard core.

Looking at the talk at FPGA on some of the arch tricks used to make the ALU so short in NIOS-1, it might be possible.

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

All,

If you can compile your code from c, who cares what the architecture is?

Sorry, but it really doesn't matter.

Speed, and ease of use are what counts in this business.

Apologies to processor architects, but unless you are doing a research project, hardly anyone cares anymore about these details.

At lunch the other day we were reminiscing about how the Z8000 never took off because they changed their architecture and instruction set completely from the Z80 and immediately alienated all of their customers (who were still programming in assembly language in those days).

Not like that anymore.

Austin

PS: check out

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Nicholas C. Weaver wrote:

Reply to
Austin Lesea

I disagree on the register window front. It is a pain if you are doing garbage collectors (you have to flush the windows), but more importantly, it DOES impact performance.

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

Ouch! I don't want to get into any marketing debates or flame wars, but I feel that inaccurate descriptions of the product I'm familiar with should be called out:

- Nios I had a 16-bit ISA. You are correct sir.

- Nios I had 32 registers per window (that is, per context), and a compiler option to make it a flat 32 registers (that has been in the kit for a couple years now). You are again correct that Nios II has a flat 32 registers.

- Nios I had JTAG-based HW & SW debugging (for some time now!)

- Nios I had a hardware divider custom instruction (in the kit!) that in two mouse clicks and a documented compiler switch had HW divides implemented.

And lest we forget:

- Avalon (off-chip memory at decent performance, anyone?)

- SOPC Builder.

- A happy user-experience implementing systems.

Regards,

Jesse Kempa Altera Corp. jkempa at altera dot com

Reply to
Jesse Kempa

"Austin Lesea" wrote

Not quite getting it into production may have troubled some customers...

The Spartan-3 of its day ;-)

Reply to
Tim

Why do you think it's wierd? I found the fast ISR entrance quite useful. I hope ISR entrance is as fast in Nios II. I heard it the windowing was thrown out because of patent issues, not on its technical merits.

-- Pete

Reply to
Peter Sommerfeld

It's creating weird situation in embedding processing where you reach the limit of the window. There should only be different 3 numbers used as sizes, 0, 1 or infinity. Any other number will creating barriers that will be reach and have impacts on the system. On reaching the limit of the register window, you have a big chunk of data to save and load which isn't nice to have when you need to have a deterministic system.

Göran

Peter Sommerfeld wrote:

Reply to
Goran Bilski

Can you explain a bit more? If you need more than 31 levels of call stack, how deterministic could your application be?

I know there is merit to what you say, as that's why NiosI has the mflat model available. I'd just like to have it explained.

Ken

Reply to
Kenneth Land

I'm headed over to payroll right now!

Eric

Reply to
Eric Crabill

Sorry, Cisco has decided to switch back to 100% ASIC, your payroll is now set to size 0. :)

--
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Reply to
Nicholas C. Weaver

I think I spotted the words 'simulated' close to that number... :) ie the standard 'release it today, but talk about how fast it will be next year....'

-jg

Reply to
Jim Granville

No, No, stooop ! They'll choose the ONE in the middle!! :)

Reply to
Jim Granville

I'm lost - since the register count is finite at around 32 in most RISC designs, how does removing a feature improve the situation ?.

I don't know the specific NIOS details, but Register window/Frame Pointer/Register Bank select schemes have been around for years, and can greatly help code density and reaction speed if done properly. I think sparc had a clever partial frame pointer, that allowed some registers to carry calling/return parameters, and some as local variables. The compiler needs 'to be on its toes', but that's a SW housekeeping issue. Another nice feature of register frame pointers, is if you are uncomfortable with them, you can just ignore it, and you have a 'vanilla RISC' core.

-jg

Reply to
Jim Granville

Tim,

Low blow.

S3 shipped a lot of parts last quarter. A whole lot of parts.

No one expected the product to gather that many orders that fast. Even the optomists among us were made to look like pessimistic fools.

If we would have only believed our own sales pitch that S3 was a better deal than an ASIC in volume (which it is), we might have been at least partially prepared.

Aust> "Austin Lesea" wrote

Reply to
Austin Lesea

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin,

1759
Reply to
Ray Andraka

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