Hi,
I was talking to an "expert" in synthesis and he mentioned that there is
a lot of difference between a synthesizable RTL code for a FPGA and a synthesizable RTL code for an ASIC.
Is this true?
If so, could you please point the significant differences between the two and what causes these differences.
Thanks, Anand
The differences is in the choices you make. In FPGAs state is cheap and logic is expensive, in ASICs logic is cheap and state is expensive. To be more specific,
FPGAs LUTs (the FPGAs logic element) are relatively slow and not very plentiful. FFs are very plentifull (relative to the available LUTs). RAM is very very plentiful, each LUT is typically worth 2-5 ASIC gates as logic but as a 16 bit RAM it's equivalent to 50-100 gates. There is also lots of RAM in the form of block RAMS. Shift registers are nearly free if you use the LUT RAM based shift register. Interconnect is very slow relative to an ASIC.
ASICs Logic gates are almost free. They are very fast relative to an FPGA so you can do much more in a cycle (unless you are running at GHz clock rates). FFs are more expensive. Each FF is 6 gates (I might be wrong about the exact gate counts here, it's been a while since I've had to think in these terms, but the orders of magnitude are correct). RAM is much more expensive. A 16 bit RAM requires 16 latches and the associated decoding and multiplexing logic. Block RAM type structures layout efficiently but they still require a lot of area, in an FPGA they are already there so you might as well use them, in an ASIC you would think about how much RAM you absolutely need and you probably wouldn't waste in on things like look up tables unless that was absolutely the best way to do the function.
They don't have to be so different.
if you design for ASIC and port to FPGA, the results will be poor as ASICs will allow for maybe 5x as much logic depth per clock cycle up to say a few 100MHz.
if you design for FPGA with equiv resources available in ASIC, the results should be good both ways, only faster for ASIC but not as much as the 5x would suggest since you will have taken advantage of what is already fast in FPGA.
When RTL is written for for HW that is easy to infer to blocks that can be mapped well onto mults,wide adders, memories, muxes, so on, the differences can be smaller. If most of the logic is unstructured and not very pipelined the differences will be much larger.
For ASICs to succeed in the future, I think it would be prudent to design for FPGA if at all possible and expect 1st pass success on ASIC and get early prototypes for months in advance of silicon.
Buts thats not always doable, where ASIC will always shine is true full customization for semi digital with some analog content. An all digital low vol 1 clock ASIC is an easy target for FPGA. The ASICs you find in very high (n Mil unit) volumes such as disk controlers, DVD players are way too cost sensitive for FPGAs to make any dent and usually require multiple and varying clock domains with some analog stuff thrown in.
For my own tastes, I'd stick to the easy path where they can be more equivalent.
regards
johnjakson_usa_com
Hi anand, I have worked on FPGA to ASIC migration.First we proved our design on Xilinx FPGA's.We used pipelining, variable & signals.During ASIC migration there were lot of warnings generated,so we replaced all variables with signals.Basically design must be very structural and synchronous.There must not be nesting of "if statements".Use clock gating to reduce power.Our design need almost 40% changes just to improve area and reduce power.
Regards, Raghavendra.S
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.