I have a EDK based design with 8 MB of external flash memory on the PLB via the plb_emc core. This is for a Virtex II Pro using EDK/ISE 7.1i, latest service packs. The flash is addressed at 0xFF800000 -0xFFFFFFFF. Thus our plan is to have the processor reset vector in the flash and execute directly from flash.
I am able to successfully use the XPS flash programming tool to burn the flash on my board in most cases I have tried. It reports the CFI info properly. However I have observed these failures (that seem to me to be related).
- If I try to burn a full 8MB image, I get an immediate parameter check that the file is larger than the flash. I have carefullly examined the file and it is exactly 8MB (8388608 bytes). If I make it
- Using the "16 bytes less than 8MB" image, if I set the offset to
- Using a 256KB image, I can burn it at any offset (well I think so
- I haven't tried them all :) ) up to 0x7BFFFF. This is up to but not including the last byte of the flash address space. If I use an offset of 0x7C0000 (This is the configuration I really need, a 256K image at the high end of flash address space. I must include the reset vector.) it fails with the error message below.
- With either size image, the offset seems to be modulo 4 i.e. offsets of 0, 1, 2, and 3 all start at the first byte of the flash address space. I suppose this is not necessarily wrong, but it is unexpected.
The error message reported is: Flashwriter Application reported and error: The flash block erase operation errored out!
I opened a web case with Xilinx and was told this:0xFFFFFFFF is hard-coded for the reset vector and cannot be accessed. It cannot be overwritten. That is why you are getting this error.
This seems wrong to me. I say this for the following reasons:
- I can load an FPGA design with BRAM at address 0xFFFFFFFC and then write any value I want to that address using a simple PPC program.
- I can load an FPGA design with Flash at address 0xFFFFFFFC and the program that location successfully with my own test code running on the PPC
- If I load an FPGA design that places the flash at 0x08000000, the XPS tool errors out in the same way as I described in the original problem statment. It reports an error trying to erase blocks, if the programming range includes the last 32 bit word.
Does anyone have any insight or experience that could help here?