hi
I am doing a research on comparing the different design methodologies for vhdl with altera maxplus2 and xilinx ise webpack software.
I am trying to find out the propagation delay ie maximum delay parameter in the synthesis report from altera maxplus2 but couldnt find it?can any body of u help me in this regard? in the maxplus2 there is one option
assign > global project timing requirements..
here we need to enter the value of the propagation time.but i thought it is some value which is decided after the design is synthesized and is available in the synthesis report as in xilinx ise webpack......
some light on this topic will be of great help to me .
thank you
shahab