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unused pins

I try to port processor in xilinx FPGA. The processor code does 've more inputs, outputs, buffers declared in entity. Now while pin assignment in ucf file, if suppose I use only some and left others, without assigning at all , will the ISE assign those left signals to pins automatically. Iam trying to download to development board, which is assigned for some processor/logic. If suppose the tool automatically assign some pins which is not intended, it may cause board problems. Am I right, give some insight, Prakash

Reply to
Prakash
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In general ,I think the tool will aotumatically remove the unused pins in the designs,but we shuld let the unused pins have the proper state,for example iin the ddr sdram if the DQM signals have hardly attached in the borad,if I don't use it in some circumstance,so we must let if high,and if we don't make it the proper state,and the data will be wrong,I don't know if I am right.

Reply to
bjzhangwn

You can always build it and see. Use the floorplanner tool to see what external pins are there. The EDK will apparently place and route all signals in its external port list (that makes sense). I doubt the ISE will route anything that is not being used.

Reply to
motty

What I thought of unused pins is to make some state, but while assigning package pins in ISE, in PACE, I couldnt assign nets to pins I need. I could see only banks(bank0,1,,) not AJ15/AC4.... . How to assign nets to pins graphically rather UCF file. Where Iam wrong, Prakash

Reply to
Prakash

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