newbie question regarding netlist resource constraint (EDIF)

Hello all,

I'm a student, I didn't have any synthesis experience before, currently I need to perform VHDL to EDIF netlist format. The netlist file should be only limited to some specific resource, for example it contains only LUT after mapping, or only AND gates or NAND gates before mapping.

I already tried two synthesis tools, Xilinx XST and Synopsys Design Compiler. I can successfully got netlist in EDIF format. However, by checking user guide, I could not find how to constraint resource to a specific set of primitives in both XST and Synopsys DC. Does anyone know if this is possible?

Thanks in advance


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Minchuan Wang
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currently I





know if

For XST, the set of primitives is defined by the selected device (project type). Xilinx has nothing to gain from offering tools that allow you to synthesize into an arbitrary set of primitives, since the point of XST is to target only Xilinx devices. That said, it is possible to restrict the output somewhat. You can disable RAM, Mux, or Shift register extraction. This is described in the online documentation (Constraints Guide). You can also force blocks to synthesize into a LUT, but the partitioning into LUTs then becomes manual. To map into only AND or NAND gates, for example, you should look for a synthesizer geared toward ASIC design rather than a (freebie) FPGA synthesizer.

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