Setup violation warning with constant signal in Modelsim/Webpack

Hi folks,

Xilinx ISE Webpack 6.3.02i (XST VHDL) Modelsim Starter 5.8c

160MHz clock

During a post par back annotated simulation I am getting the following warnings occuring about 40/50 times (i.e. not all the time and they are occuring after the reset phase is over):

# ** Warning: /X_SFF SETUP High VIOLATION ON CE WITH RESPECT TO CLK; # Expected := 0.095 ns; Observed := 0.088 ns; At : 111.338 ns # Time: 111338 ps Iteration: 2 Instance: /filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424 # ** Warning: /X_SFF SETUP Low VIOLATION ON CE WITH RESPECT TO CLK; # Expected := 0.095 ns; Observed := 0.088 ns; At : 117.588 ns # Time: 117588 ps Iteration: 2 Instance: /filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424

The strange thing is that the CE signal in question is hard-coded to 1 in the port mapping like this:

DualPortCyclicRAMBuffer : DualPortCyclicBuffer

generic map ( DATA_DEPTH => FILTER_LENGTH )

port map (

clk => clk, ce => '1', reset => reset, rfs => rfs, nsi => nsi, dataIn => x, dataOut1stHalf => cyclicRAMDataOut, dataOut2ndHalf => cyclicRAMDataOutDualPort, finalSample => cyclicRAMFinalSample, sor => cyclicRAMSOR );

So, how can there be setup violations on a signal that doesn't change?

Can I just ignore this?

Many thanks for your time and insight.



Reply to
Loading thread data ...


did you check in the par vhd file that the ce input of the instance:


is stuck to 1? did you see that signal stuck to 1 during simulation at the time indicated in the warnings (111.338 ns and 117.588) ?


Reply to
Andrea Sabatini

The CE pin of the instance /filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424 may not be the same "ce" connected to your component instantiation.

HTH, Jim (remove capital letters)

formatting link

Reply to
Jim Wu

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.