Hello
I have one modul which is written in Verilog, which I wanna add to my IP core written in VHDL. The simulation works fine, but when I want to synthesize it, XST tells me that it doesnt find the verilog file...
Can somebody please tell me how to handle this problem? my .pao file looks like this
lib fsl_ff3_v1_00_n constants
lib fsl_ff3_v1_00_n memory
lib fsl_ff3_v1_00_n controller
lib fsl_ff3_v1_00_n coprocessor
lib fsl_ff3_v1_00_n ff3_alu
lib fsl_ff3_v1_00_n add
lib fsl_ff3_v1_00_n sub
lib fsl_ff3_v1_00_n gf3.v
lib fsl_ff3_v1_00_n ff3
lib fsl_ff3_v1_00_n multiplexer
And I always get the error message that it cant find gf3.v.vhd. So how can I tell EDK that this time I have a verilog and not a vhdl file?
Thanks for your help
Philipp