DDR2 Memory Design: Layout, timing

you can obtain the ml461 sch from xilinx I think

hmm.. MIG 1.5 and EDK ??

EDK 8.1 SP1 has non-MIG based DDR2 support, I have not heard that EDK will include support for MIG generated memory cores?

Antti

Which DDR devices are you going to use? Whatever they are, get the data sheets and start a timing budget analysis.

For most impedance controlled tracks on FR4 (or something close), signal transit time is about 160picosec / inch. For the timing budget, you need to know the timing *at the pins* (which can differ significantly from the signal at the IO buffer).

For each standard via, add 50 picoseconds (minimum) of deterministic jitter at edge rates.

The schematics are simply not sufficient for setting layout rules - you need a precision data sheet with all the relevant timing parameters listed.

Cheers

PeteS

hello PeteS, I like to use all kind of DDR2 Ram modules fitting in the DDR2 SoDIMM Socket (200pin). I looked at the micron page and found the data sheet for MT8HTF6464HD. Actually there are no timing information. When I use instead the information from the micron chips on the module itself, I need to add something for the traces on the module. I think the absolute trace length doesnt matter - the Xilinx MIG core compensates for that. Maybe I need to buy the ML461 Reference Board from Xilinx. Are there any layout rules? Are the schematics included? does anybody have the layout rules and schematics?

thanks pit

Try this datasheet:

It's a typical DDR2 device from Micron and has *tons* of timing specs.

Absolute length to the device does matter for a number of reasons (deterministic jitter being one of them, turnaround time being another) although if the core can take care of the turnaround timing it will help.

For the timing budget, there are two budgets that are inter-related

1. CK/#CK to address / command
2. CK/#CK to data.

1. is unidirectional and fairly simple.

1. is bidirectional and not simple at all.

To give you an idea of what is involved: Read: The various Dn lines will have some skew across them (and relative to DQS as an output) that must be subtracted from the timing budget. All clock to data uncertainties must be subtracted. All timing uncertainties in the core relative to read data must be subtracted. Write: All timing uncertainties in the core relative to write must be subtracted. All timing uncertainties in the DDR2 relative to latching data must be subtracted.

After all that, you get to figure out how much mismatch you are permitted in the board on the D[group] as a group, D[group] vs. CK, CK

- #CK, CK to address/command and so forth.

The last time I set up a timing error budget it took me a couple of days just to set the budget.

Cheers

PeteS

For impedances, see the IBIS models. I usually use 60 ohm tracks and terminate into 50 ohms to Vref for address, series terminate in the middle for short traces on data (although you can get away with no termination on point to point **if** you can set the drivers at each end to be about 60 ohm impedance (which is possible on the DDR device through the extended mode register) and by setting the output drive on the FPGA core (or setting Rtt bits if available).

Note if you do this, your Vref driver needs to be able to source *and* sink current.

CK//#CK should be differentially terminated as close to the DDR device pins as possible, normally into about 100 ohms, but this depends on the driver.

It's possible a SODIMM will already have the terminators onboard, but you need to check. There should be some guidance on the effective impedance of the system.

Cheers

PeteS