XILINX System Generator "fatal error"

Hi all,

using sysgen from Xilinx and inserting an Chipscope block the code generation will stop with a "fatal error" giving me the advice to look for help on the Xilinx support page. But there was no such help. Maybe I can find it here. The project for ISE is generated with some files missing, belonging to the Chipscope core. I have installed all the software properly in version 6.1i (ISE, Chipscope, Sysgen) so I don't know the reason sysgen behaves like that. Any solutions are welcome. But don't tell me to reinstall all, I wont do that - again ...

Jan

Reply to
Jan Losansky
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Jan, I have not used sysgen but on occasion I have had problems with chipscope in regular ISE 6.1. These problems usually stem from selecting an ineligible signal to be sampled or as the trigger or as the clock. You could eliminate this theory by minimzing your chipscope selections and only selecting signals you are sure are valid.

Good luck

Matt

Reply to
Matthew E Rosenthal

Matt, thank you for your answer. But I even tried it on a simple design with two inputs an XOR an one output trigerring on one input and measuring it. Still the same behavior. I have checked an example provided by Xilinx too with no change. I probably have to call someone at Xilinx.

Jan

"Matthew E Rosenthal" schrieb im Newsbeitrag news: snipped-for-privacy@unix49.andrew.cmu.edu...

Reply to
Jan Losansky

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