problem in driving I2C bus through memory-mapped register

Apr 01, 2005 10 Replies

Hi,



I have an fpga which is accessed from ARM as a memory-mapped device.



A register in fpga is used to drive a I2C bus connected to a device . Two bits in the register represent clock and data lines of the bus.



When I try to write into this register from ARM software as shown below, write is not happening. ARM is running at 48 Mhz.



int* reg = 0x44400030;



*reg = 0x3;

The above code is not able to modify the register.



But when I write using Lauterbach trace32 command as shown below, it works.



data.set SD:0x44400030 %LE %LONG 0x3



What could be the reason ?



Please advise. thanks shankar



Possibly, missed "volatile" qualifier.

Vadim Borshchev

Try this:

int* reg = (int*)0x44400030;

*reg = 0x3;

Regis.

Or this:

int* reg = (int*)0x44400030;

*reg = 0x3L;

Regis ( snipped-for-privacy@dacafe.com)

Have you previously written the same value to that location ? If so, it's possible that your compiler spots the duplication and doesn't do it a second time (unless you write something else in between).

This is because "int" refers to a "variable" and not a memory location, per se. The difference is that writing to a memory location can have a side effect. This is what you want, so you may need to stick a "volatile" qualifier in, to make sure the compiler really does do a write.

Richard [in PE12]

I recommend that you look at the compiler output, either through an assembly listing or, better yet, through the disassembly output of a debugger. See what code is being generated. Compare that to what you know works. This is a powerful technique that all programmers, but especially embedded systems programmers and systems programmers can benefit from.

It might have something to do with memory mapping or the width of the write, but those are just guesses.

Thad

Thanks to all who replied.

I forgot to add that the same C code works when executed from an ARM core which is part of the same fpga which contains the I2C register

So the code is perfect.

We analysed the memory access signals such as chip select, write enable, wait etc using a TLA . They look OK.

The wait signal comes as an input to the memory controller peripheral of ARM from the fpga.

thanks

Let me add that there are other memory mapped registers on the fpga . I have a problem only accessing the I2C related register.

In terms of execution flow, what is the difference between memory access through : a) Trace32 JTAG debugger and b) code running on arm ?

As I said, the memory access works through jtag debugger Trace32.

What is the difference in execution flow of memory access through debugger command and software instruction ? This is the key to solve this problem.

snipped-for-privacy@gmail.com wrote in news: snipped-for-privacy@l41g2000cwc.googlegroups.com:

stepping the code will cause a drain of the write buffer on every instruction to syncronize 'memory', Your first post has expired here - so I don't know what core you are using. Is the write buffer coelessing?

I use ARM9

I had tried not stepping thru also.

What does coelessing mean ?

thanks

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