Xilinx Read First Write First

If you write to mem[addr] the same clock edge that you read mem[addr] on that same port, what do you want for the result?

Do you want the old data before the write as if it were a register (read first) or the brand new data that's in process of being written to the memory array (write first)? The Xilinx Software Manuals (library guide) have the tables that try to explain the nuances.

So, I'm reading and writing on the same clock. I suppose if I wanted to do this, maybe for speed, I would want the read to be the old data before the write. Can't think of any reason I would want the new data going in. I already have it.

do

A fall-through FIFO is one example where the data going in might be needed on the output. If the memory is for storage of values, why not use the most recent value with a write-first?

Fixed delay-lines are easy to implement with a single address with read first.

do

Any Virtex BlockRAM always performs a "free" read operation whenever you do a write. The data appearing at the data output is either the data previously stored at that location (and about to be oberwritten), or it is the data you are just writing, or the data output does not change, keeps holding its old value. You pick one of these three choices by configuration.

The Virtex-4 FIFO has an optional "fall-through" mode, where data written into an empty FIFO immediately appears on the read output port. Responding to a different thread: The Virtex-4 FIFO generate FULL and EMPTY flags and ALMOST FULL and ALMOST EMPTY flags, all internally synchronized (rising and falling edges) to the relevant clock domain. We just finished testing asynchronous operation at 500 MHz read clock rate, with no error in

Peter Alfke, Xilinx Applications

It's mainly for compatibility with the behavior of the first BlockRAMs. Nobody suggests that you should use it in newer designs... Peter Alfke

Got it. Thanks.

Neat. Thanks.

Can you measure the metastability parameters?

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How about dual port BRAM? My understanding is that both the ports have access to the same BRAM. So if in through one port you want to read the data and through the other port you want to write the data to same memory location what will happen?

Thanks

This is called "you get what you deserve" mode.

This is explaind in detail here:

Philip Freidin

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for

In dp_block_mem.pdf, it states: The Spartan-II/Virtex and Virtex-II/Spartan-3 block memory is True Dual-Port RAM that allows both ports to simultaneously access the same memory location. When one port writes to a given memory location, the other port must not address that memory location (for a write/read) within the clock-to-clock setup window. Note that conflicts do not cause any physical damage to BlockRAM cells. For more information on conflict resolution, refer to the Spartan-II, VIrtex, Virtex-II/Spartan-3 Databook available at the website:

In coregen, after one selects the particular IP, there is a "Data Sheet" button that links information about the IP block. The above was taken directly from the "Data Sheet"

- Newman

Thanks for the reply. I read the data sheet and it clarified all the queries I had. I am just quoting the same here.

For synchornous clocks.

1. If both ports read simultaneously from the same memory cell: Both Data_out ports will have the same data.

2.If both ports write simultaneously into the same memory cell: The data stored in that cell becomes invalid (unless both ports write identical data).

1. If one port writes and the other port reads from the same memory cell: The write operation succeeds, and the data to be read out from the read port will be determined by the read output mode