Dear all, Normally SDRAM needs tens of MS to refresh bank of memory,while what happens when I happened to visit this memory address,either read or write. Dose the SDRAM controller(say,IP core from Xilinx) makes this read/write operation waiting for this refresh period and execute read/write command afterwards(That's unacceptable in term of time or speed for this read/write operation!)? Or it handles such condition in another way? Thanks for your information. regards
- posted
19 years ago