Hi all, what is the max frequency you have achieved with TSMC 18um library. I an trying to synthesise a design at 528Mhz(1.8ns). Design Compier results shows that the synthesis timing constraints were met. But when I do netlist simulations I am getting 1000's of timing violations...I checked the verilog simulaton model for the library and found that the setup and hold checks are done in the library for 1ns ... ie for a clock edge I need 1+1 ns for just satisying the setup hold constraints... well my doubt is why the DC tool says the timing constraints are met.. do you have any idea.
thanks whizkid