How to ensure Select signal arrives after Input signals changed

Question

Hello,I have a problem Routing a design in Xilinx ISE 8.2. I found a failurecaused by a multiplexer where the Select signal arrives slightly afterone of the input signals changed. This causes a narrow pulse in theoutput data line of the multiplexer. When this pulse arrives to thenext register, the setup time is ok, but it suddenly falls violatingthe hold time. This problem does not appear in post-map simulations, soI guess it is exclusively due to some skew between Select and Inputlines, introduced at the routing stage.I don't understand why the router allows this to happen. It would beeasy to check routes and throw warnings when an Input data path islonger than the Select path. However, the static timing analysis is okat all stages, no constraints violations.Does anyone know how can I solve this issue? I'm sure many peoplefought with this before...Thanks in advance.

Frai · Accepted Answer

Just one correction over previous post: the Select signal arrivesslightly BEFORE the Input signal changes, and not after as I said.Regards.

Mike Treseler · Answer

Static timing verifies that each max delay from Q to D is less than 1/Fmax. It knows nothing of your intentions. I work that part out with Modelsim. Maybe the design is not synchronous, or if it is, the mux path is not set up at least one tick before the input change.

-- Mike Treseler

How to ensure Select signal arrives after Input signals changed

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