How to ensure Select signal arrives after Input signals changed


I have a problem Routing a design in Xilinx ISE 8.2. I found a failure caused by a multiplexer where the Select signal arrives slightly after one of the input signals changed. This causes a narrow pulse in the output data line of the multiplexer. When this pulse arrives to the next register, the setup time is ok, but it suddenly falls violating the hold time. This problem does not appear in post-map simulations, so I guess it is exclusively due to some skew between Select and Input lines, introduced at the routing stage.

I don't understand why the router allows this to happen. It would be easy to check routes and throw warnings when an Input data path is longer than the Select path. However, the static timing analysis is ok at all stages, no constraints violations.

Does anyone know how can I solve this issue? I'm sure many people fought with this before...

Thanks in advance.

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Just one correction over previous post: the Select signal arrives slightly BEFORE the Input signal changes, and not after as I said.


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Static timing verifies that each max delay from Q to D is less than 1/Fmax. It knows nothing of your intentions. I work that part out with Modelsim. Maybe the design is not synchronous, or if it is, the mux path is not set up at least one tick before the input change.

-- Mike Treseler

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Mike Treseler

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