hi, I'm working with ISE6.3.03i I want to run my design at 160MHZ. So I put this contraints on my .ucf file : Clk = 6.25ns Offset in = 6.25 ns; Offset out = 6.25 ns In my place end route report, I have 'All constraints are met". But when I run my design wih ModelSim some Hold and Setup error occur. So I watch the timing report (Post Place And Route). I have something like that :
setup hold ARST 4.683 3.136 ENI -0.455 3.489 SRST 3.786 3.514 WRCFG 1.424 4.196 .... ... ...
The setup time is the time the input must be stable before the clock edge. If there was a large logic delay between the signal pin and the register, the input to the part could change before the clock edge, and the delay in the logic would keep the input to the register stable until after the clock edge.
The hold time should almost always be negative. If external logic changes inputs to the part right after the clock edge, and the worst case hold time is positive, then what data will be seen by the part? The data before the clock edge? Or the data after the clock edge?
Design. Make all inputs registered before any logic. Make all outputs registered after any logic. If this can't be done, more care is needed.
Constraints. If external logic outputs a signal after a clock edge by some delay, and the board trace delays the signal by ~80 ps/cm, and the clock to the external logic might be after the clock to the part, then the input constraint must be less than the clock period. How much less? Work it out on a signal by signal basis. Do the same for output signals.
-- Phil Hays Phil-hays at posting domain (- .net + .com) should work for email
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