Nios Clock Frequency

Hello,

Can't really help you right now, but I'm extremely interested in this particular topic.

We're about to start a Nios on Cyclone project and I'm expecting to get at least 50MHz operation. Now I'm really curious!

I'm troubled that Altera posts little or no performance information on Nios whereas Xilinx posts 85MHz (Spartan3) and even gives benchmark scores for its MicroBlaze offering.

Perhaps someone knows what configuration options lead to the highest performance on Nios. We'll see....

Ken

Hi Ken,

Nios

It's fairly easy to reach 50MHz with a NIOS core on a Cyclone. The standard

32-bit design, which is pretty dressed-up, easily meets this requirement. I've had fairly minimal systems run way over 75MHz (actually, 98MHz) on an EP1C6T144C7 (medium speed grade). Of course, if you have a big nonpipelined multiplier or some other long combinatorial path in the rest of the FPGA, this is going to affect ytour clock speed as well.

Best regards,

Ben

Hi Maxlim,

Sounds like a memory timing problem or somesuch. I suggest you contact your local disti or Altera FAE on how to check for I/O timing problems.

Best regards,

Ben

Quartus compilation results - does the design meet your 50MHz requirement? Wait-state, setup, and hold time values for the off-chip peripherals

Hello, Thanks for fast response. The message in the Quartus compilation report is all timing requirement is met. The version of Quartus and SOPC Builder I'm using now is 2.2 SP2 and 3.02. I'm not adding interface to the user defined peripheral or adding the peripheral into the SOPC library. It's difficult to communicate or access the peripheral through the memory map allocated by SOPC Builder due to unknown arrangement of the I/O port. I'm using the primitive way by adding PIO interface to the system for communication between the nios and user processor. It seem like the error will occur while the system try to transfer data to the host pc through UART. Is it the wrong setting in the UART that cause this problem?

Hi Ben,

I'm new to the processor on FPGA world (been using Coldfire) and was only lightly involved with the FPGA stuff on our previous designs. (added a few features and fixed a few bugs in an Altera 7000MAX)

Anyway, my question concerns your statement about "in the rest of the FPGA". My understanding is/was that FPGA logic that is not specifically tied to together in the FPGA runs independently. For example I assume that I can have two (or more) Nios processors running completely independently on the same FPGA with little effect unless I choose to tie their logic together.

I appreciate your comments.

Ken

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nonpipelined

Hi Jesse,

Thank you for your valuable info. I'm looking forward to tweaking my Nios to the max. The ability to add custom logic and instructions to achieve desired performance is a major draw for us.

Are there any other forums that may be more Nios specific? I could imagine Nios and SOPC builder generating a lot of traffic on their own.

Ken