location constraint doubt

In one of the ucf file I could see these. I could understand the logic element dll0 is constrained to be placed at DCM_X2Y1. I could see there are more such DCM_X#Y#. How can I associate for my chip, means how can I select the # for my chip. Also here dll0/1 is constrained two times. Is it to make absolute/relative paths of them so that approprite software can take.

INST "clkgen0_v_dll0" LOC = DCM_X2Y1; INST "clkgen0_v_dll1" LOC = DCM_X1Y1; INST "clkgen0/xc2v.v/dll0" LOC = DCM_X2Y1; INST "clkgen0/xc2v.v/sd0.dll1" LOC = DCM_X1Y1;

Prakash

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Prakash
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The only thing special about the locations of the DCMs is what clock input pins they are near or what partial or global clock buffers they drive. Your design will often have physical constraints for pin placement which, in turn, drives where the logic will typically be placed. The ins and outs of the DCMs in your design are best physically associated with the input pin and driven logic. The device has a specific number of resources with explicit XY locations; you can leave it to the tool to find a decent solution (no LOC constraints) or make the decision based on your knowledge of the design.

Sometimes it's helpful to run the design without DCM LOC constraints, see if the results are acceptable, then copy the DCM locations for that place & route run into your constraints.

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John_H

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