DDR2 vs SDR on Spartan3

Hi to all,

I am considering to replace the x16 SDRAM for a x16 DDR2 to gain some bandwidth for a MicroBlaze system. I wonder if someone tested the Xilinx EDK MCH_OPB_DDR2 memory controller core for bandwidth on Spartan3. Looking at the MCH_OPB_DDR2 datasheet It apears that burst reads are not performed every clock cycle?! Is that true? I tested OPB_SDRAM controller at 50MHz and the measured bandwidth is about 60MB/s using burst transfers (poor) and reads are performed every 4th cycle. Another problem with OPB_SDRAM is no support for async clocking so RAM is always clocked at OPB clock.

Comments and suggestions welcome,

Guru

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Guru
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DUHH, no, no, no !!! Use mch_opb_sdram !!

opb_sdram is a very simple (slow slow) SDRAM controller that you can use when you want to read a byte or something, nothing more. Try mch_opb_sdram, it supports bursts and plays nice with the xilinx DMA core, you get more bandwidth and it interfaces with the microblaze's cache.

Since you apparently have a board with SDRAM, instantiating mch_opb_sdram is easy, and it's a lot faster than opb_sdram. Try it ;)

Reply to
PFC

use

DMA

mch_opb_sdram

PFC,

I guess you dont know what is behind these two controllers. The SDRAM controller is the SAME for both of them. The OPB_SDRAM works the same as the MCH_OPB_SDRAM if you connect it only to OPB bus. If you want Microblaze to have a fast access to SDRAM then you use MCH otherwise it is a waste of logic resources.

Guru

Reply to
Guru

You made me doubt ;) I had a look again at the timing diagrams of both controllers and here is the explanation :

I am using a dual port BRAM. One port is connected to a core I wrote which gets data from the outside world, and writes it to the BRAM. The other port is connected to opb through the appropriate Xilinx core. This is a kind of FIFO. So I wanted to copy data using DMA from BRAM to SDRAM fast in order to empty my FIFO and not hog the OPB bus too much since there are a lot of other stuff running. OPB is 32 bits @ 50 MHz so max bandwidth is 200 MB/s, but in real life it will be lower of course.

You say opb_sdram and mch_opb_sdram have the same SDRAM controller core ; I trust you on that, but this isn't my point... the key is how those lock the OPB bus (or not).

When doing burst-write to opb_sdram, the OPB bus is locked during almost the entire transaction. However, mch_opb_sdram has a FIFO : it will absorb the OPB burst write, then the OPB bus is free for other stuff while the SDRAM core writes to the memory. Obviously you can't access SDRAM since the controller is busy, but you can still use OPB to access BRAM or other things.

Here is how it went with mch_sdram

- DMA controller writes a burst to opb_sdram

- opb_sdram keeps the OPB bus to itself while it writes to the SDRAM chip

- after the write is finished, OPB is now available

- DMA controller reads from BRAM

- repeat

Here is how it went with mch_opb_sdram

1 - DMA controller writes a burst to mch_opb_sdram which fills its FIFO 2 - concurrently : - DMA controller refills its buffer from BRAM via OPB bus which is free - mch_opb_sdram flushes its FIFO to the SDRAM chip 3 - repeat

So, if you want to burst data from some OPB peripheral or BRAM to SDRAM, the mch controller will be much faster. DMA copy from SDRAM to SDRAM, or SDRAM reads, won't show much difference though.

Reply to
PFC

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